Through Interconnect Via Reducing Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing integrated circuits while maintaining effective interconnectivity and reducing resistance, as current methods for forming through interconnect vias in multilayer dielectric structures are inefficient, leading to high contact resistance and signal transmission issues.
Innovation Solution
The formation of a through interconnect via (TIV) that penetrates multiple dielectric layers, with a conductive filling material occupying most of the volume and a barrier layer occupying a smaller portion, reducing resistance and improving signal transmission by increasing the cross-sectional area and volume of the conductive filling material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via formation methods are used in multilayer dielectric structures, then manufacturing simplicity is maintained, but contact resistance increases and signal transmission performance deteriorates
Solution Approach 1:
The via formation process is segmented into distinct stages: forming openings through dielectric layers, depositing barrier layers, and filling with conductive materials. This segmentation allows optimization of each stage independently, achieving low resistance while maintaining manufacturing feasibility through standardized process modules.
Solution Approach 2:
The invention transitions from planar interconnect structures to three-dimensional through-via structures that penetrate multiple dielectric layers. This dimensional change enables vertical signal transmission paths, reducing resistance by creating direct conductive routes through the stack rather than relying on lateral connections.
2Reliability
If the cross-sectional area of via structures is increased to reduce resistance, then contact resistance decreases, but the volume occupied by barrier material increases
Solution Approach 1:
The barrier layer is applied selectively only at the sidewalls and bottom of via openings, rather than filling the entire via volume. This local application provides necessary electrical isolation and adhesion functions while minimizing barrier material consumption, allowing larger via cross-sections for lower resistance without proportionally increasing barrier material volume.
Solution Approach 2:
The via structure employs a composite configuration with distinct functional layers: barrier layers (titanium nitride, tantalum nitride) for electrical isolation, and conductive fill materials (copper, cobalt, tungsten) for low-resistance transmission. This composite approach optimizes the balance between resistance reduction and material usage by assigning specific functions to each material component.
Data Source
AI summary
Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.