Through-Latch Semiconductor Storage Device Address Latching Method
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-speed DDR systems, the sharing of input pins for address and command signals leads to an access penalty due to fetching data on both rising and falling edges, resulting in increased access time by half the clock period (½ tCK), which existing technologies have not effectively addressed.
Innovation Solution
Implementing a semiconductor storage device with a through-latch-type latch circuit that latches address data on the falling edge of a clock signal and command data on the rising edge, reducing the access time and penalty associated with the edge-trigger-type latch circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an edge-trigger-type latch circuit is used to fetch command data and address data on rising and falling edges, then the latch circuit can operate with shared input pins, but the access time increases by half the clock period (½ tCK) due to the access penalty
Solution Approach 1:
The latch circuit is segmented into two independent through-latch-type latch circuits: one for latching command data on rising edges and another for latching address data on falling edges. This segmentation allows each latch to operate independently with optimized timing, eliminating the access penalty associated with a single edge-triggered latch handling both signals.
Solution Approach 2:
Different latch circuits are assigned different latching characteristics tailored to their specific functions: the command data latch uses rising edge triggering while the address data latch uses falling edge triggering. This local optimization of latching characteristics for different signal types enables reduced access time while maintaining shared pin capability.
2Productivity
If data are fetched both on rising and falling edges in the high-speed system, then the access efficiency can be improved, but the access penalty of ½ tCK occurs as shown in FIG. 10
Solution Approach 1:
The fetching operation is segmented into two independent processes: command data fetching on rising edges and address data fetching on falling edges. Each process uses its own dedicated through-latch-type latch circuit, allowing simultaneous operations without the time penalty incurred by a single latch circuit attempting to handle both signals.
Solution Approach 2:
The through-latch-type latch circuits are designed to latch data in advance of when the data are fully stable, utilizing the setup time before the clock edge. This preliminary latching action reduces the effective access penalty by preparing the latched data ready for immediate use without waiting for the full clock period.
3Loss of time
If a through-latch-type latch circuit is used to latch address data on the falling edge, then the access time from the falling edge can be reduced by setup time, but the circuit complexity increases compared to a single edge-trigger-type latch
Solution Approach 1:
The latch function is segmented into two separate through-latch-type latch circuits rather than using a single edge-triggered latch. While this increases the number of latch components, each latch is simpler in structure and can be implemented with standard through-latch cells, making the overall complexity manageable while achieving significant time reduction.
Solution Approach 2:
Each latch circuit is optimized locally for its specific function: the command data latch is optimized for rising edge triggering while the address data latch is optimized for falling edge triggering. This local optimization allows each latch to operate at maximum efficiency for its purpose, reducing the overall system complexity compared to a single latch attempting to handle both functions.
Data Source
AI summary
A semiconductor storage device includes: an input buffer that receives address data and command data; a first through-latch-type latch circuit that latches the command data in synchronism with a rising edge of a clock signal; and a second through-latch-type latch circuit that latches the address data in synchronism with a falling edge of the clock signal.