Semiconductor Interconnect Structure With Through-Layer Power Rail Vias
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a smaller area, including issues with leakage and the need for improved interconnect structures to enhance performance and efficiency.
Innovation Solution
The formation of semiconductor devices with a device layer between front-side and back-side interconnect structures, where conductive vias connect conductive features of the back-side interconnect structure to the front-side interconnect structure, using conductive features instead of semiconductive features to improve performance by reducing resistance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but leakage and performance issues worsen
Solution Approach 1:
The patent introduces a dual-sided interconnect architecture where conductive vias penetrate through the substrate to connect front-side and back-side interconnect structures. This three-dimensional vertical interconnection approach allows signal and power routing in the depth dimension, enabling higher integration density on the surface while maintaining reliable electrical connections through the substrate to mitigate leakage issues.
Solution Approach 2:
The patent employs an intermediate substrate layer with through-substrate vias that act as mediators between front-side and back-side interconnect structures. These conductive vias serve as intermediary pathways that directly connect corresponding conductive features across the substrate, providing controlled low-resistance paths that reduce leakage and improve signal integrity while enabling dense component integration.
2Ease of manufacture
If conventional semiconductive features are used for interconnection, then manufacturing is simpler, but resistance and parasitic capacitance increase reducing performance
Solution Approach 1:
The patent changes the material parameter of interconnect features from semiconductive to conductive materials. By using highly conductive materials for the via fills and interconnect structures, the patent achieves significantly lower resistance and parasitic capacitance values, thereby improving signal transmission performance and power efficiency while maintaining manufacturing feasibility through standard conductive deposition processes.
3Productivity
If more components are integrated into smaller area, then device density increases, but interconnection complexity and leakage increase
Solution Approach 1:
The patent resolves interconnection complexity by utilizing the vertical dimension through the substrate. Instead of routing all interconnections laterally across the dense chip surface, conductive vias provide direct vertical pathways through the substrate, connecting front-side and back-side interconnect structures. This three-dimensional routing approach simplifies the interconnection architecture by eliminating the need for complex multi-layer lateral routing while supporting high component density.
Data Source
AI summary
In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.