Through Level Vias Connecting Non-Consecutive Metal Levels
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Solution Overview
Problem
The challenge in semiconductor technology is to minimize process variations and misalignment errors in forming through level vias while maintaining yield and performance, as wider metal lines to accommodate vias lead to reduced spacing between metal lines, causing yield and reliability issues.
Innovation Solution
The solution involves forming through level vias that directly connect metal lines across non-consecutive metal levels, using a structure with an outer barrier layer and an inner core filled with conductive material, which minimizes misalignment by etching metal lines wider than vias and maintains adequate spacing between metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal lines are patterned wider near and above vias to minimize misalignment errors, then misalignment errors are reduced, but spacing between metal lines is reduced causing yield or performance loss
Solution Approach 1:
The patent introduces through-level vias that extend vertically across multiple metal levels (e.g., from metal level 1 to metal level 3), adding a vertical dimension to the via structure. This allows the via to span multiple levels without requiring excessive lateral widening of metal lines, thus maintaining spacing while achieving alignment tolerance across non-consecutive levels.
Solution Approach 2:
The patent uses an intermediary metal level (metal level 2) as a mediator between non-consecutive metal levels. The through-level via passes through this intermediary level, allowing electrical connection between metal level 1 and metal level 3 without requiring direct alignment between them, thereby reducing the need for widened metal lines.
2Productivity
If through level vias are formed to connect non-consecutive metal levels, then interconnect efficiency is improved, but process complexity increases
Solution Approach 1:
The patent merges the formation of through-level vias with the existing via formation process for consecutive levels. By using the same etch and fill processes that are already established for forming vias between adjacent metal levels, the patent avoids adding significant process complexity while achieving the benefit of direct connections across non-consecutive levels.
Data Source
AI summary
In one embodiment, a semiconductor device includes a first metal line disposed in a first metal level above a substrate. A second metal line is disposed in a second metal level disposed over the first metal level. A third metal line is disposed in a third metal level disposed over the second metal level. A through level via contacts the first metal line and the third metal line.