Semiconductor Through-Line Repair via Test Pulse Signals
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Solution Overview
Problem
Conventional semiconductor chip repair methods are inefficient due to the occupation of substantial space by repair fuses and the inability to effectively repair defects in semiconductor chip through-lines, which can lead to potential failures.
Innovation Solution
A semiconductor apparatus and method that utilize test pulse signal transmission units and reception units to detect defects in semiconductor chip through-lines during power-up operations, allowing for the repair of these lines using redundancy through-lines without the need for repair fuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repair fuses are used to repair semiconductor chip through-lines, then defects can be repaired, but substantial area is occupied
Solution Approach 1:
The patent extracts the repair functionality from the traditional repair fuse structure and relocates it to the test pulse signal transmission units and reception units. By using test pulse signals to detect and repair defects in semiconductor chip through-lines, the system eliminates the need for dedicated repair fuse areas, thereby resolving the contradiction between defect repair capability and area occupation.
Solution Approach 2:
The test pulse signal transmission units and reception units serve multiple functions: they can transmit test pulse signals for defect detection, receive and process the transmitted signals, and enable repair operations. This multi-functionality allows the system to perform defect repair without requiring separate repair fuse structures, thus reducing the area occupied while maintaining reliability.
2Reliability
If conventional repair schemes are used, then some defects can be repaired, but defects in semiconductor chip through-lines that may potentially occur cannot be repaired
Solution Approach 1:
The patent implements preliminary action by performing defect detection using test pulse signals before actual operation. The test pulse signal transmission units transmit signals through the semiconductor chip through-lines during power-up operations, allowing potential defects to be identified and repaired in advance, thereby expanding the coverage of repairable defects while maintaining a relatively simple repair scheme.
Solution Approach 2:
The reception units receive the test pulse signals transmitted through the semiconductor chip through-lines and provide feedback information about the signal transmission status. This feedback mechanism enables the system to identify defects accurately and initiate repair operations, thereby improving defect repair coverage while keeping the repair scheme manageable through systematic signal transmission and reception processes.
3Reliability
If repair operations are performed using test equipment, then defects can be detected and repaired, but the process is time-consuming and requires external equipment
Solution Approach 1:
The patent implements self-service by enabling the semiconductor apparatus to perform its own defect detection and repair operations using integrated test pulse signal transmission units and reception units. During power-up operations, the system automatically transmits test pulse signals, detects defects, and performs repairs without requiring external test equipment, thereby reducing the time required for repair operations while maintaining reliable defect detection and repair capabilities.
Data Source
AI summary
A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units.