Through Mold Connectors for High Density Semiconductor Packages

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Solution Overview

Problem

The challenge lies in integrating multiple semiconductor devices into a single package structure to achieve high functionality and small size, while ensuring efficient electrical connectivity and manufacturing efficiency, particularly in package-on-package (PoP) structures where existing methods face limitations in reducing bump size and increasing I/O paths without increasing package size.

Innovation Solution

The method involves forming a semiconductor package with a stepped mold layer structure, where a first mold layer covers a semiconductor chip and bumps, exposing top portions of the bumps, and then forming a second mold layer to connect additional bumps, creating a through mold connector (TMC) that penetrates both layers, allowing for increased height and reduced bump diameter, enabling more efficient electrical connectivity and higher I/O density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If multiple semiconductor devices are integrated into a single package structure to reduce size and increase functionality, then the package size is reduced and functionality is enhanced, but the manufacturing complexity and process difficulty increase

Engineering Contradiction:
Improvepackage sizeVSAvoidmanufacturing complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The package structure is divided into multiple layers (first mold layer, second mold layer) with distinct functional regions. The first mold layer contains first bumps for electrical connection, while the second mold layer contains second bumps forming through-mold connectors. This segmentation allows complex multi-device integration to be managed through modular layer-by-layer construction, reducing overall manufacturing complexity while achieving high functionality in a compact size.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If bump size is reduced to increase I/O paths in a given package area, then I/O density is increased, but the electrical connectivity and signal integrity deteriorate

Engineering Contradiction:
ImproveI/O densityVSAvoidelectrical connectivity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The invention transitions from a single-layer bump arrangement to a multi-layer three-dimensional structure. Through-mold connectors extend vertically through both the first and second mold layers, creating additional electrical connection paths in the vertical dimension. This allows increased I/O density on the package surface while maintaining robust electrical connectivity through the extended vertical connector structure, effectively decoupling the trade-off between bump size reduction and connectivity maintenance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If a through mold connector is formed to penetrate multiple layers, then electrical connectivity and I/O paths are enhanced, but the manufacturing process time and complexity increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidprocess time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The first bumps are formed and positioned in the first mold layer before the second mold layer is applied. This preliminary action establishes the electrical connection foundation early in the process. Subsequently, the second mold layer with second bumps is formed over the first layer, and the through-mold connectors are created by penetrating both layers. This sequential preliminary action approach allows the complex multi-layer connector structure to be built efficiently through staged manufacturing operations rather than requiring simultaneous complex processing, thereby reducing overall process time while maintaining enhanced electrical connectivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9922965B2Manufacturing methods semiconductor packages including through mold connectors
Publication Date: 2018.03.20 MIMIRIP LLC
  • US9922965B2 patent drawing
  • US9922965B2 patent drawing
  • US9922965B2 patent drawing

AI summary

A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.