Through-Mold Via Die Stack Layout for Shorter Signal Paths

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Solution Overview

Problem

Conventional semiconductor packages face challenges with signal crowding and long data paths, which limit data rates and increase the footprint of vertically stacked dies.

Innovation Solution

The implementation of through mold vias (TMVs) and fan-out redistribution layers (FO RDLs) allows for bidirectional high-speed signal conveyance between dies in a die stack and a redistribution structure, reducing the data path length and minimizing the package footprint.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If vertically stacking semiconductor dies is implemented to increase processing power, then functional capacity increases, but package footprint increases

Engineering Contradiction:
Improveprocessing powerVSAvoidpackage footprint
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The patent transitions signal routing from a planar two-dimensional path to a three-dimensional path by routing signals through the thickness of the molding compound via through-mold vias. This vertical routing approach in the third dimension reduces the lateral footprint required for signal interconnection while maintaining the vertical stacking architecture for increased processing power.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If conventional electrical connectors and interconnects are used to couple dies, then electrical connection is achieved, but data path length increases limiting data rate

Engineering Contradiction:
Improveelectrical connectionVSAvoiddata rate
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent extracts the signal routing function from the traditional planar path through die interconnects and relocates it to a vertical path through the molding compound using through-mold vias. This separation of routing functions reduces the data path length by eliminating unnecessary lateral signal travel through multiple interconnect layers, thereby increasing data rate while maintaining reliable electrical connection.

Inventive Principle:
Principle #2Taking out (Extraction)

3Speed

If through silicon vias are used to reduce data path length, then data rate increases, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvedata rateVSAvoidmanufacturing complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent replaces expensive through silicon vias with through-mold vias formed in the molding compound. The molding compound, being a polymeric material, is more easily processed for via formation using standard PCB drilling and plating techniques. This substitution maintains the short data path length benefit for high data rates while significantly reducing manufacturing complexity and cost by using more accessible fabrication processes.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS12230608B2Semiconductor assemblies with system and methods for conveying signals using through mold vias
Publication Date: 2025.02.18 MICRON TECHNOLOGY INC
  • US12230608B2 patent drawing
  • US12230608B2 patent drawing
  • US12230608B2 patent drawing

AI summary

A semiconductor device has first and second dies forming a die stack. Molding material encapsulates the die stack and forms an upper molded surface of the die stack. First conductive traces are coupled to the first die and extend from between the first and second die to corresponding first via locations in the molding material beyond a first side edge of the die stack. Second conductive traces coupled to an active surface of the second die opposite the first die extend to corresponding second via locations. Each first via location is vertically aligned with one of the second via locations. Through mold vias extend through the molding material between vertically aligned via locations to contact with corresponding conductive traces of the first and second dies, while the molding material that extends between the first conductive traces and the upper molded surface is free from any TMV.