Through-Mold Via Package Structure for High-I/O Die Stacking
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Solution Overview
Problem
The challenge in semiconductor devices is to maximize the number of input/output terminals in a reduced size format while minimizing space, as the smaller size restricts the availability of input/output terminals, particularly when using solder balls, which complicates the formation and stacking of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a substrate with a conductive pattern and through-mold vias that provide electrical signal paths from the exterior surface to the substrate and between semiconductor dies, allowing for increased input/output terminals and enabling efficient stacking and connection of additional semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of the semiconductor device is reduced, then the space needed to accommodate the device is minimized, but the available space for input/output terminals is restricted
Solution Approach 1:
The patent transitions from planar input/output terminals to three-dimensional vertical stacking architecture. By stacking multiple semiconductor dies vertically and providing input/output terminals on both upper and lower surfaces, the device achieves increased terminal capacity without increasing footprint area, effectively resolving the contradiction between reduced device size and increased number of input/output terminals
Solution Approach 2:
The patent implements nested stacking of multiple semiconductor dies within a compact package body. Smaller semiconductor dies are stacked vertically one on top of another, with each die nested within the overall package structure. This nesting approach maximizes the number of terminals within a reduced volume by utilizing the vertical dimension
2Quantity of substance
If plural semiconductor dies are stacked in a single semiconductor device, then the number of input/output terminals is increased, but the available space for forming these terminals is limited
Solution Approach 1:
The patent utilizes the vertical dimension by stacking semiconductor dies in the Z-direction rather than expanding in the X-Y plane. This dimensional transition allows multiple dies to be accommodated within a compact footprint, increasing terminal count without proportionally increasing the space required for terminal formation
3Volume of moving object
If the size of the semiconductor device is reduced, then space efficiency is improved, but it becomes difficult to realize various functions due to insufficient availability of input/output terminals
Solution Approach 1:
The patent nests multiple functional semiconductor dies within a single compact package, with each die potentially performing different functions. The vertical stacking arrangement allows diverse functionality to be integrated without increasing the device footprint, thereby maintaining space efficiency while enhancing adaptability and versatility
Solution Approach 2:
The stacked semiconductor device structure enables multi-functionality by integrating multiple dies with different functions within a single package. The universal stacking architecture can accommodate various types of semiconductor dies, allowing the device to perform multiple functions simultaneously while maintaining a reduced size
Data Source
AI summary
In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.