Through-Package Partial Vias on Package Edge for Signal Integrity
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Solution Overview
Problem
Integrated circuit (IC) packages face challenges in maximizing I/O counts, data processing speed, and signal integrity due to the space consumed by embedded interconnects in package-on-package assemblies, which limits floorplan space and increases conductor path length, thereby affecting resistance and signal integrity.
Innovation Solution
The implementation of through-package partial vias (half vias) on the edges of chip packages, which are electrically coupled to the substrates, providing efficient routing paths between packages with reduced substrate space usage and lower resistance compared to embedded interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded interconnects are used in package-on-package assemblies, then electrical connectivity between packages is achieved, but floorplan space is consumed and conductor path length increases
Solution Approach 1:
The patent moves conductive vias from the embedded interior of the package substrate to the edges/boundaries of the substrate. This dimensional relocation allows vias to be positioned at the periphery rather than consuming central floorplan area, thereby maintaining electrical connectivity while preserving valuable internal space for other package components.
Solution Approach 2:
The patent extracts the conductive via structure from the embedded interconnect layer and repositions it to the package edge. By taking out the via from its traditional embedded position and relocating it to the boundary region, the design eliminates space consumption in the package interior while maintaining the electrical connection function.
2Reliability
If embedded interconnects are used in package-on-package assemblies, then electrical connectivity is provided, but conductor path length increases and resistance increases
Solution Approach 1:
By relocating vias to the edge of the substrate, the patent creates more direct, shorter conductive paths between corresponding points on stacked packages. The peripheral positioning reduces the lateral distance signals must travel compared to embedded vias that require longer routing through the substrate interior, thereby reducing overall conductor path length and associated resistance.
3Speed
If more I/O connections are added to increase data processing speed, then signal integrity may be improved, but floorplan space is further constrained
Solution Approach 1:
The patent utilizes the peripheral region of the substrate by positioning conductive vias at the edges, effectively converting unused boundary space into functional I/O connection points. This allows additional I/O connections to be added without encroaching on the central floorplan area needed for die placement and other critical package components, thereby supporting higher data processing rates while maintaining space efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances floorplan space utilization, reduces conductor path length, and improves signal and power integrity by enabling fan-out wafer-level package-on-package assemblies with lower resistance and fewer interfaces, thus scaling down the chip package form factor and enhancing electrical connectivity.
Implementation Method 1
plating the one or more cavities with a conductive material, wherein the one or more plated cavities are electrically coupled to at least one of the first substrate or the second substrate
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.