Through-Plate Interconnect for Vertical MIM Capacitor Routing
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Solution Overview
Problem
Conventional approaches for connecting vertical metal-insulator-metal (MIM) capacitors to memory cell logic require complex and costly special routing and patterning, especially when the capacitor is not located at the top of a dielectric layer, leading to increased area usage and fabrication complexity.
Innovation Solution
A through plate interconnect method that allows direct connection of the MIM capacitor to memory cell circuitry by using a via that extends parallel to the capacitor, eliminating the need for special patterning and reducing area requirements, enabling modular insertion and efficient pairing with transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a via is touched down on the top plate to make the connection, then the top plate electrode can be connected to memory cell logic, but this approach is of limited use where the top plate electrode is located in a place other than the top of a dielectric layer
Solution Approach 1:
The patent transitions from a conventional planar via connection (single dimension) to a three-dimensional stacked architecture where the capacitor can be positioned at various heights within the dielectric layers. The connection is achieved through vertical vias that extend through multiple dielectric layers, enabling the capacitor to be located in different spatial positions while maintaining electrical connectivity to memory cell logic.
2Ease of operation
If special routing and patterning are used to connect the capacitor plate to memory cell logic, then the connection can be made, but the area usage increases and fabrication complexity increases
Solution Approach 1:
The patent merges the capacitor structure with the memory cell logic by integrating them within the same vertical stack. The capacitor plates are formed within the dielectric layers surrounding the memory cell transistor, and connections are made through shared vias that serve both the capacitor and the logic circuitry, thereby reducing the overall device area compared to separate routing paths.
Solution Approach 2:
The invention utilizes the vertical dimension to position the capacitor above or below the memory cell logic rather than requiring lateral routing. This vertical stacking approach reduces the planar footprint by exploiting the third dimension, allowing denser integration without increasing the lateral device area.
3Ease of operation
If special routing and patterning are used to connect the capacitor plate to memory cell logic, then the connection can be made, but the device complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming the memory cell logic first, then forming the capacitor plates within the dielectric layers, and finally creating the connecting vias. This segmentation allows each component to be optimized independently while simplifying the overall fabrication process compared to simultaneous complex patterning of both capacitor and logic connections.
Solution Approach 2:
The dielectric layers are formed and prepared in advance before the capacitor plates and connecting vias are created. This preliminary preparation of the dielectric structure provides a ready-made framework that guides subsequent capacitor formation and via creation, reducing the complexity of coordinating multiple patterning steps.
Data Source
AI summary
An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.