Through-Polymer Via Fabrication via Inverted Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing via manufacturing processes for 3D semiconductor stacking and integration, such as TSVs and TMVs, face challenges like conformal coverage of complex surfaces, filling of narrow high-aspect-ratio structures, wafer thinning, and material property mismatches, leading to difficulties in accurate placement and electrical connection.
Innovation Solution
A 'via first' process involving a microstructure of polymer coated with a conducting material and encapsulated in an insulating material, allowing for the integration of semiconductor devices and systems in a single step, using photoresist and electro- or electroless-plating techniques, which enables precise and cost-effective high-aspect-ratio via creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to establish electrical connections, then vertical interconnection is achieved, but manufacturing complexity increases due to conformal coverage requirements, filling of narrow high-aspect-ratio structures, and material property mismatch
Solution Approach 1:
Instead of forming vias through the substrate first and then adding conductive material (TSV approach), the patent inverts the sequence by first creating the conductive interconnect structure and then forming the insulating substrate around it. This is achieved by depositing conductive material on a carrier substrate, patterning it into interconnect structures, and finally forming the insulating layer that encapsulates these structures, thereby eliminating the need for complex via formation processes.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the conductive interconnect structures on the carrier substrate before creating the final device structure. The conductive material is deposited, patterned, and prepared in advance, allowing subsequent steps to simply encapsulate these pre-formed interconnects rather than forming them through complex via processes.
2Ease of manufacture
If through mold vias (TMVs) with large diameter channels are used, then via formation is simplified, but resistance increases and suitability for 3D integration decreases
Solution Approach 1:
The patent changes the parameters of the conductive interconnect structures by controlling the deposition thickness and patterning dimensions to achieve optimal dimensions. The conductive material is deposited in controlled layers and patterned to create interconnect structures with dimensions that provide low resistance while maintaining ease of manufacture, avoiding both the high resistance of large-diameter TMVs and the manufacturing complexity of narrow TSVs.
3Ease of manufacture
If wafer thinning is performed to accommodate TSV fabrication, then via formation becomes possible, but wafer cracking occurs due to material property mismatch
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary element that supports the formation of conductive interconnect structures. This carrier substrate serves as a stable platform that eliminates the need to thin the final device wafer, as the interconnect structures are formed on the carrier and then transferred or encapsulated with the final wafer structure, thereby preventing wafer cracking.
4Manufacturing precision
If accurate placement of TSV interposer is required, then electrical connection precision is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent merges the formation of conductive interconnect structures with the substrate fabrication process itself. By forming the conductive structures on the carrier substrate and then encapsulating them with the insulating layer that becomes part of the final device structure, the placement precision is achieved through integrated process control rather than separate alignment steps, reducing overall manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates low-cost, large-scale fabrication of high-aspect-ratio vias with reduced manufacturing complexity, lower resistance, and miniaturization capabilities, suitable for 3D integration, packaging, and heterogeneous systems, offering improved signal transmission and interconnect performance.
Implementation Method 1
Wherein the polymer is a photoresist. Examples of suitable photoresists include SU-8 and dry film photoresist laminate... exposing the photoresist to a suitable wavelength of radiation (typically UV or even x-ray); exposing the photoresist to a suitable photoresist developer
Implementation Method 2
coating the microstructure with a layer of a first electrically conducting material... using photoresist and electro- or electroless-plating techniques
Implementation Method 3
using photoresist and electro- or electroless-plating techniques
Data Source
Figure 1(a)~1(i)
Figure 2
AI summary
The invention relates to vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers. In particular, the invention relates to a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers i.e. in an out-of-plane direction.