Through-Silicon Buried Power Rail for Backside Power Reliability
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Solution Overview
Problem
The manufacturing of backside power distribution network (BSPDN) semiconductor architectures faces challenges such as misalignment between buried power rails and through-silicon vias, leading to increased resistance and device failure, as well as thermal degradation of metal buried power rails during front-end-of-line processing.
Innovation Solution
A method of manufacturing a BSPDN semiconductor architecture that includes forming a carrier substrate with patterned fins and oxide layers, creating trenches and filling them with metal to form a buried power rail that extends from one surface to the other, eliminating the need for a separate through-silicon via and reducing thermal degradation by forming the BPR after FEOL layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate through-silicon via is used to connect the buried power rail to the backside power distribution network, then the power delivery path is established, but misalignment between the via and power rail occurs leading to increased resistance and device failure
Solution Approach 1:
The patent merges the through-silicon via formation process with the buried power rail formation process by etching both structures simultaneously through the substrate. This integration eliminates the separate alignment step between via and power rail, as they are formed as a unified structure in the same etching process, thereby resolving the misalignment issue and improving device reliability
Solution Approach 2:
The patent performs preliminary patterning of both the buried power rail and through-silicon via openings before etching. By pre-defining the positions and dimensions of both structures using photolithography and etch stop layers, the subsequent etching process can proceed simultaneously for both structures without alignment issues, as the positions are predetermined and protected by the etch stop layers
2Productivity
If the buried power rail is formed prior to front-end-of-line processing, then the power distribution network is established early, but thermal degradation occurs during high-temperature FEOL processing leading to metal migration and diffusion
Solution Approach 1:
The patent applies preliminary protective measures by depositing conformal dielectric layers and performing planarization over the buried power rail before FEOL processing. These protective layers act as thermal barriers and physical protection during subsequent high-temperature steps, preventing metal migration and diffusion while allowing the power rail structure to be established early in the manufacturing process
Solution Approach 2:
The patent modifies the physical and chemical parameters of the buried power rail structure by applying conformal dielectric coatings and performing chemical-mechanical polishing. These parameter changes create a protected structure that can withstand the thermal conditions of FEOL processing without experiencing metal migration or diffusion, thus maintaining thermal stability while enabling early formation
Data Source
AI summary
Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.