Through-Silicon Via Formation for Precise Buried Rail Alignment
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Solution Overview
Problem
The challenges of integrating through semiconductor via connections (TSVs) in semiconductor processing include alignment issues due to wafer distortion during bonding, pattern deformation, and insufficient contact area between buried power rails and TSVs, particularly in high-density metallized structures, which affect the resistivity and connectivity of power delivery networks.
Innovation Solution
A method involving etching via openings from the front side of a semiconductor substrate, filling them with a sacrificial material, bonding the substrate face down to a carrier, thinning the bulk wafer, and removing the sacrificial material to create a through semiconductor via connection, ensuring precise alignment and increased contact area by forming a conductive pad integral with buried interconnect rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If via-last approach is used with wafer bonding, then TSV connections are formed, but alignment precision deteriorates due to wafer distortion and pattern deformation
Solution Approach 1:
The patent applies preliminary action by forming the TSV openings and filling them with conductive material before the wafer bonding step. This sequence ensures that the TSV structures are already in place and can serve as alignment references during bonding, preventing the alignment issues that occur when trying to compensate for distortion after bonding. The TSVs are formed through the substrate before bonding to the carrier, establishing a stable geometric reference framework.
2Productivity
If high density metallized structures are used, then device density increases, but contact area between buried power rails and TSVs decreases
Solution Approach 1:
The patent resolves the contact area limitation by extending the conductive structure laterally beyond the TSV opening. Instead of relying solely on the vertical TSV-conductors interface, the conductive material forms a pad or extended region that increases the contact footprint in the lateral dimension. This dimensional extension allows sufficient contact area even when TSV spacing is reduced for high density applications.
3Ease of manufacture
If TSVs are formed after bonding, then process integration is simplified, but alignment accuracy deteriorates due to non-linear wafer distortion
Solution Approach 1:
The patent performs the TSV formation operations before the bonding step, establishing the conductive pathways and structural references in advance. This preliminary formation of TSVs through the substrate creates a stable geometric framework that remains unchanged during bonding, eliminating the need for complex distortion compensation algorithms and enabling accurate alignment.
4Manufacturing precision
If TSVs are formed from frontside, then alignment to buried rails is improved, but contact area to backside structures is reduced
Solution Approach 1:
The patent compensates for the reduced contact area from frontside formation by extending the conductive material laterally at the backside interface. The TSV opening is filled with conductive material that spreads out to form an extended pad or footprint, increasing the contact area with backside structures in the lateral dimension while maintaining the alignment precision achieved through frontside formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves alignment and connectivity by maintaining precise alignment of TSVs with frontside buried interconnects, reducing resistivity, and enhancing the contact area, thereby improving the efficiency of power delivery networks in semiconductor chips.
Implementation Method 1
an etch stop layer... suitable for stopping the removal of the bulk semiconductor wafer by etching
Implementation Method 2
bonding the substrate face down to a carrier
Data Source
AI summary
The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.