Through-Silicon Via Structure Using Double-Sided Plasma Etching

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Solution Overview

Problem

Conventional through silicon via manufacturing processes face inefficiencies due to low etching rates and material waste, particularly in the thinning of silicon wafers and the deep etching required for three-dimensional integrated circuit packaging, which affects production efficiency and increases costs.

Innovation Solution

The method involves hydrogen ion implantation to lift off silicon wafers, followed by double-sided plasma etching to form through silicon vias, and subsequent deposition of insulating and conductive layers, eliminating the need for chemical-mechanical polishing and optimizing the etching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If mechanical grinding is used to thin silicon wafers, then the overall thickness of the package is reduced, but a considerable thickness of silicon material is removed without being recycled, resulting in material waste

Engineering Contradiction:
Improvethickness of silicon waferVSAvoidsilicon material waste
Core Design Contradiction:
Length of stationary objectVSLoss of substance

Solution Approach 1:

The patent replaces mechanical grinding with chemical etching processes (wet etching and vapor HF etching) to remove silicon material. This substitution allows for more precise control of material removal and reduces waste by enabling selective etching of only the necessary portions to achieve the desired thickness and through-via formation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the physical and chemical parameters of the silicon wafer processing by using controlled chemical reactions instead of mechanical forces. By adjusting etching parameters such as chemical concentration, temperature, and exposure time, the desired thickness reduction is achieved with minimal material waste.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the silicon wafer is etched on one side only, then the through silicon via is formed, but the etching rate is rather low, affecting production efficiency

Engineering Contradiction:
Improvethrough silicon via formationVSAvoidproduction efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent divides the etching process into two separate sides, allowing simultaneous or sequential etching from both the front and back of the silicon wafer. This segmentation of the etching operation effectively doubles the material removal rate while maintaining precise control over through-via formation, thereby improving production efficiency without sacrificing manufacturing precision.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances etching rates, reduces material waste, and simplifies the manufacturing process, leading to higher production efficiency and lower costs while maintaining high performance in three-dimensional integrated circuit packaging.

Implementation Method 1

lifting off a silicon wafer by implanting hydrogen ions into the silicon wafer to obtain a substrate for making a through silicon via

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

performing double-sided plasma etching on the substrate to form a through silicon via penetrating the substrate

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 3

electroplating a conductive metal material into the through silicon via

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11887912B2Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof
Publication Date: 2024.01.30 SHANGHAI INTEGRATED CIRCUIT MFG INNOVATION CENT CO LTD
  • US11887912B2 patent drawing
  • US11887912B2 patent drawing
  • US11887912B2 patent drawing

AI summary

The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof. The method of the present disclosure includes the following steps: lifting off a silicon wafer by implanting hydrogen ions into the silicon wafer to obtain a substrate for making a through silicon via; performing double-sided plasma etching on the substrate to form a through silicon via penetrating the substrate; depositing an insulating medium, a copper diffusion barrier layer, and a seed layer; and removing parts of the copper diffusion barrier layer and the seed layer by photolithography and etching processes, leaving only parts of the copper diffusion barrier layer and the seed layer on a sidewall of the through silicon via; forming a sacrificial layer on the upper and lower surfaces of the resulting structure, completely filling in the through silicon via with conductive metal material, and then removing the sacrificial layer, upper and lower surfaces of the conductive metal material respectively protruding from upper and lower surfaces of the insulating medium; and forming a contact pad on a surface of the conductive metal material. The present disclosure can effectively improve production efficiency and lower the cost.