Through-Stack Thermal Sink Layout for Dense Dual-Sided ICs
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to optimize performance while managing thermal management and power delivery in high-density, high-power applications, particularly as device dimensions scale below the 10 nanometer node.
Innovation Solution
The introduction of a through-stack thermal sink (TST) provides a thermal conductive via that extends from the device layer to the carrier wafer, improving thermal management and heat dissipation. This is achieved by etching via-like structures through the entire device stack, filling them with thermal conductive material, and landing on the silicon carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity and functional unit density increase, but thermal management becomes more difficult and device performance deteriorates due to heat accumulation
Solution Approach 1:
The patent introduces through-stack thermal sinks that extend vertically through multiple device layers, transitioning from planar heat dissipation to three-dimensional thermal management. This vertical dimension allows heat to be conducted away from dense device regions through dedicated thermal pathways, resolving the contradiction between high device density and effective thermal management.
Solution Approach 2:
The patent introduces intermediate thermal sink structures and thermal conductive materials as mediators between heat-generating devices and heat dissipation paths. These intermediate elements facilitate efficient heat transfer through the stack, enabling thermal management in high-density configurations without requiring direct device-to-heat-sink contact.
2Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but power network resistance increases leading to performance degradation
Solution Approach 1:
The patent implements power delivery networks that utilize vertical pathways through the stack, complementing traditional planar power distribution. This three-dimensional power network architecture reduces current path lengths and resistance by providing multiple parallel conduction paths, thereby maintaining reliability as device density increases.
Solution Approach 2:
The patent segments the power network into multiple distributed power delivery paths through the stack, rather than relying on single long current paths. This segmentation creates parallel conduction channels that reduce overall network resistance and improve power delivery efficiency in high-density device configurations.
3Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing complexity decreases, but thermal management and power delivery performance worsen
Solution Approach 1:
The patent introduces vertical through-stack thermal sinks that penetrate through the bulk silicon substrate and device layers, adding a three-dimensional thermal management capability to conventional planar bulk silicon devices. This allows cost-effective bulk silicon substrates to achieve improved thermal performance without requiring complex substrate modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The through-stack thermal sink enhances thermal management, leading to improved device performance with a higher throttle temperature limit and better thermomechanical reliability. This results in significant reductions in power network resistance and improved performance, allowing for reduced cell height and increased frequency without significant power increases.
Implementation Method 1
The introduction of a through-stack thermal sink (TST) provides a thermal conductive via that extends from the device layer to the carrier wafer, improving thermal management and heat dissipation
Data Source
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AI summary
Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.