Through-Stack Thermal Sink Layout for Dual-Sided IC Heat Dissipation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit manufacturing is to optimize performance while managing thermal management and power delivery in high-density, high-power applications, particularly as device dimensions scale below the 10 nanometer node.
Innovation Solution
The introduction of a through-stack thermal sink (TST) provides a thermal sink and heat dissipation path from the device to the carrier wafer, improving thermal management and reducing throttle temperature limits, thereby enhancing device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity and functional unit density are improved, but thermal management becomes increasingly difficult and device performance deteriorates due to heat accumulation
Solution Approach 1:
The patent introduces a through-stack thermal sink that extends vertically through multiple device layers, transitioning from planar heat dissipation to three-dimensional thermal management. This vertical thermal pathway enables heat to be conducted away from dense device regions through the stack depth, effectively managing thermal loads in high-density 3D integrated circuits without compromising device performance
2Quantity of substance
If the number of functional units is increased on limited chip area, then capacity is improved, but thermal throttling increases and device reliability deteriorates
Solution Approach 1:
The through-stack thermal sink utilizes the vertical dimension to provide dedicated thermal management pathways that extend through the entire device stack. This enables high-density functional units to be packed on the chip area while maintaining reliable operation by conducting heat away through the vertical stack structure, preventing thermal throttling and ensuring device reliability
3Quantity of substance
If device dimensions are scaled below 10 nanometer node, then capacity is improved, but thermal throttling increases and performance is compromised
Solution Approach 1:
The patent implements a through-stack thermal sink that provides vertical heat conduction pathways through the device stack, enabling effective thermal management in sub-10 nanometer technology nodes. This three-dimensional thermal management approach allows aggressive device scaling for increased capacity while maintaining performance by preventing heat accumulation through the vertical thermal pathways
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a through-stack thermal sink effectively reduces thermal throttling, improves thermomechanical reliability, and allows for more aggressive scaling of device dimensions without compromising performance.
Implementation Method 1
provides a thermal sink and heat dissipation path from the device to the carrier wafer
Data Source
AI summary
Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.