3D Stacked Semiconductor Package With Overlap-Tuned Through Structures
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Solution Overview
Problem
There is a need for improved semiconductor packages with a 3D stacked structure that efficiently connects multiple semiconductor chips while minimizing electrical resistance and electromigration deterioration, particularly in the context of increasing power density and miniaturization demands.
Innovation Solution
The semiconductor package includes a first semiconductor chip with a substrate, lower and upper wiring layers, and through structures that electrically couple these layers, along with external connection terminals, where the through structures overlap with wiring patterns within a specific pitch distance to optimize power delivery and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If through structures are positioned to overlap wiring patterns within half the pitch distance, then electrical resistance is reduced and power delivery efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-defining the optimal overlapping position of through structures relative to wiring patterns during the design stage. The specification of 'half pitch distance' as the overlapping distance establishes a predetermined alignment rule that guides subsequent manufacturing processes, ensuring that through structures are positioned to maximize electrical connection efficiency while maintaining manufacturability.
Solution Approach 2:
The patent utilizes parameter changes by optimizing the spatial relationship between through structures and wiring patterns. By specifying that through structures overlap wiring patterns within 'half the pitch distance,' the patent transforms the geometric parameters of the interconnection structure to achieve lower electrical resistance. This parameter optimization balances electrical performance improvement with manufacturing capability.
2Power
If multiple semiconductor chips are stacked in a 3D structure, then power density and integration capacity increase, but thermal management difficulty and electromigration deterioration increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from traditional planar interconnections to three-dimensional stacked chip architecture. By stacking semiconductor chips vertically and implementing through structures that penetrate multiple layers, the patent achieves higher power density and integration capacity. The overlapping configuration of through structures with wiring patterns in the vertical dimension optimizes electrical pathways, reducing electromigration effects despite increased power density.
3Use of energy by moving object
If through structures overlap wiring patterns within half pitch distance, then power delivery efficiency is enhanced, but device complexity increases
Solution Approach 1:
The patent applies merging by combining multiple functions into the through structures. These structures simultaneously serve as mechanical support elements, electrical connection pathways, and alignment references for wiring patterns. By integrating these functions into a single structural element with a standardized overlapping configuration, the patent reduces overall device complexity while maintaining enhanced power delivery efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances power delivery efficiency, reduces electrical resistance and electromigration deterioration, and allows for higher power density integration in a compact form factor.
Implementation Method 1
a plurality of through structures electrically coupling the lower wiring layer to the upper wiring layer and penetrating the substrate
Data Source
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AI summary
A semiconductor package includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a plurality of external connection terminals electrically coupled to a lower surface of the first semiconductor chip. The first semiconductor chip includes a substrate including the lower surface and an opposite upper surface, a lower wiring layer in a lower portion of the lower surface including a first plurality of wiring patterns, an upper wiring layer in an upper portion of the upper surface including a second plurality of wiring patterns, a plurality of through structures electrically coupling the lower wiring layer to the upper wiring layer and penetrating the substrate, and a macro cell disposed between the plurality of through structures. At least one of the through structures partially overlaps a wiring pattern of the lower wiring layer in a vertical direction within an overlapping distance from the wiring pattern.