Through-Substrate Conducting Routes for High-Density Chip Packages
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Solution Overview
Problem
The challenge in chip packaging is to form a desired conducting route within a limited space while maintaining the quality of the formed route, especially as chip size shrinks and interconnection density increases.
Innovation Solution
A method involving a substrate with conducting pads, where holes and recesses are formed to create a through-substrate conducting structure, with an insulating layer and conducting layer deposited on the sidewalls and bottom of the holes, allowing for efficient electrical contact with the pads, and a protection layer to prevent damage during dicing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chip size is reduced and interconnection density is increased, then the compactness and integration of the chip package is improved, but the manufacturing precision and quality of conducting routes deteriorate due to limited space
Solution Approach 1:
The patent transitions from planar conducting routes to three-dimensional vertical conducting routes by forming holes through the substrate and stacking conducting layers at different depths. This dimensional change allows multiple conducting routes to be packed vertically within the limited chip area, achieving high interconnection density while maintaining manufacturing precision through standardized hole formation and layer deposition processes
Solution Approach 2:
The patent implements nested conducting layers within the substrate structure, where multiple conducting layers are stacked inside the substrate thickness. Each conducting layer is positioned at different depths and connected through vertical vias, creating a nested configuration that maximizes the use of limited space while maintaining clear separation and electrical isolation between different conducting routes
2Quantity of substance
If more conducting routes are formed in limited space, then the interconnection density is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent divides the conducting route formation process into discrete segments: substrate hole formation, insulating layer deposition, conducting layer deposition, and via formation. Each segment can be independently optimized and controlled, allowing complex three-dimensional conducting structures to be built through repeated application of simple, well-controlled process steps rather than attempting to form all routes in a single complex operation
Solution Approach 2:
The patent performs preliminary substrate preparation including forming the substrate structure and conducting pads before creating the holes and depositing conducting layers. This preliminary action establishes a stable foundation that simplifies subsequent steps, as the substrate and pads are pre-configured to receive the vertical conducting routes, reducing the complexity of coordinating all manufacturing steps simultaneously
3Reliability
If holes and recesses are formed to create through-substrate conducting structure, then the electrical connection reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the substrate and conducting layers, and between different conducting layers. This insulating layer serves as a mediator that provides electrical isolation, mechanical support, and alignment reference, allowing holes and recesses to be formed with relaxed precision requirements while still achieving reliable electrical connections through the conducting layers that are deposited conformally on the insulating surfaces
Data Source
AI summary
An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.