Through-Substrate Source/Drain Contact Layout for Lower Resistance
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Solution Overview
Problem
As semiconductor devices shrink, forming backside power rails and through-substrate source/drain contacts becomes challenging due to increased complexity and risk of damaging source/drain features, and existing structures provide insufficient silicide contact areas, leading to high contact resistance and parasitic capacitance.
Innovation Solution
A method involving the formation of a through-substrate source/drain contact that extends between channel members on a backside dielectric layer, using epitaxial features to reduce contact resistance, and a silicide layer to enhance conductivity, while avoiding direct etching of source/drain features, thus reducing the risk of damage and improving power delivery network performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing backside source/drain contact structures are used, then manufacturing simplicity can be maintained, but the silicide contact area is insufficient leading to high contact resistance
Solution Approach 1:
The patent transitions from planar contact structures to three-dimensional structures by forming contacts that extend through the substrate thickness and engage with vertically stacked source/drain regions. This dimensional change increases the effective contact area and reduces contact resistance while maintaining a relatively simple top-down fabrication approach.
Solution Approach 2:
The patent implements nested structures where silicide layers are formed within and around the through-substrate contacts, creating concentric zones of conductive material. This nesting approach maximizes the silicide contact area within the available vertical space, thereby reducing contact resistance without requiring lateral expansion of the contact footprint.
2Ease of manufacture
If existing backside power rail formation processes are used, then process simplicity can be maintained, but the silicide contact area is insufficient leading to high parasitic capacitance
Solution Approach 1:
The patent forms power rails with vertical extensions that penetrate through or near the source/drain regions, utilizing the third dimension to increase the effective contact area. This vertical dimensionality reduces parasitic capacitance by spreading the capacitive coupling over a larger area, thereby reducing the capacitance density.
Solution Approach 2:
The patent applies different material compositions and structural configurations to different regions of the power rails. Specifically, silicide layers are selectively formed in regions where contact with source/drain structures occurs, while other regions maintain simpler metal compositions. This local differentiation optimizes electrical properties where needed while maintaining manufacturing simplicity overall.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced contact resistance and enhanced power delivery network performance by avoiding separate backside source contact openings and engaging epitaxial features for increased interfacial areas, thereby improving the semiconductor device's efficiency and reliability.
Implementation Method 1
a silicide layer disposed between the plurality of epitaxial features and the through-substrate contact
Implementation Method 2
engaging epitaxial features for increased interfacial areas
Data Source
AI summary
A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.