Through-Substrate Metal Interconnect Layout for Low-Loss IC Routing
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Solution Overview
Problem
Integrated circuit (IC) structures face challenges in minimizing electrical loss due to unwanted resistance and inductance from elongated vertically-oriented interconnects, such as through silicon vias (TSVs), which connect devices on the front side of a substrate to metallic features on the back side, leading to inefficiencies in signal transmission.
Innovation Solution
The implementation of a through-metal through-substrate interconnect that extends vertically from a device-level metallic feature on the front side of the substrate through the substrate and interlayer dielectric material to connect with both lower and upper metallic features, reducing electrical loss by minimizing resistance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon via (TSV) interconnects are used to connect front side devices to back side metallic features, then electrical connection is achieved, but resistance and inductance increase leading to electrical loss
Solution Approach 1:
The interconnect path is segmented into multiple portions: a first portion extending from the front surface through the substrate to the back surface, a second portion extending from the back surface through the first dielectric layer to the metallic feature, and an optional third portion extending upward through the second dielectric layer. This segmentation allows optimization of each segment's contribution to resistance and inductance.
Solution Approach 2:
The invention transitions from conventional planar interconnect layouts to a three-dimensional vertical interconnect structure. By utilizing the vertical dimension through multi-layer dielectric stacks and extended via paths, the design achieves shorter current paths and reduced parasitic effects compared to traditional two-dimensional routing.
2Ease of operation
If elongated vertically-oriented interconnects are used, then substrate penetration and connection are achieved, but inductance increases reducing signal transmission efficiency
Solution Approach 1:
The interconnect structure employs nested dielectric layers where the first dielectric layer contains the metallic feature and the second dielectric layer overlays it. The interconnect portions are nested within these dielectric layers, creating a compact multi-layer configuration that reduces overall inductance while maintaining structural integrity.
Solution Approach 2:
The dielectric layers and metallic features are prepared and positioned before the interconnect formation is completed. This preliminary arrangement of layers and features allows for optimized interconnect routing that minimizes inductance from the outset, rather than requiring post-fabrication adjustments.
Data Source
AI summary
Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.