Through-Substrate Routing Via Structure for Wafer-Level Packaging
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Solution Overview
Problem
Integration of multiple semiconductor devices in wafer-level packaging poses challenges due to the complexity of forming efficient redistribution structures across the substrate, particularly in creating symmetrical and asymmetrical structures with high aspect ratio through holes, which affects the adhesion and conductivity of the semiconductor package.
Innovation Solution
A manufacturing method involving dual-side sputtering of seed and barrier layers within through holes of a substrate, where one side is initially masked as blind holes, allowing for asymmetrical redistribution structures and reduced material diffusion, and the use of composite seed-barrier layers to enhance adhesion and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual-side sputtering of seed and barrier layers is performed within through holes, then adhesion and conductivity of redistribution structures are improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent applies preliminary action by forming barrier layers and seed layers on the sidewalls of through holes before forming the redistribution structures. This sequence ensures that the conductive material has proper adhesion and conductivity from the outset, preventing subsequent failures and reducing the need for additional corrective steps in the manufacturing process.
Solution Approach 2:
The patent segments the formation of redistribution structures into distinct steps: forming barrier layers, forming seed layers, and then forming conductive material. This segmentation allows each layer to be optimized independently for its specific function (adhesion, conductivity, structural integrity), thereby improving overall reliability while making the complex process more manageable and controllable.
2Productivity
If symmetrical and asymmetrical redistribution structures with high aspect ratio through holes are formed, then integration efficiency of multiple semiconductor devices is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by forming barrier layers and seed layers specifically on the sidewalls of through holes where they are most needed for adhesion and conductivity. This localized approach ensures high precision is applied only where critical, while other areas can be manufactured with standard tolerances, thereby improving integration efficiency without uniformly increasing precision requirements across the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient formation of semiconductor packages with interconnected redistribution structures across the substrate, improving adhesion and reducing material diffusion, thus enhancing the integration and connectivity of semiconductor devices within the package.
Implementation Method 1
A first barrier material is sputtered on the substrate, from the side of the first surface. A first seed material is sputtered on the first barrier material.
Implementation Method 2
A first conductive material is plated on the first seed material while the through hole is still plugged.
Data Source
AI summary
Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.