Self-Aligned Through-Substrate Interconnects for Lower RC Delay
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Solution Overview
Problem
The increasing complexity of interconnect structures in semiconductor devices due to high transistor density leads to parasitic capacitance and increased resistance, which negatively impacts device performance by increasing power consumption and reducing switching speed.
Innovation Solution
A self-aligned interconnect structure (SIS) is introduced, which allows for the manufacture of semiconductor devices using a single manufacturing flow, reducing manufacturing complexity and eliminating the need for separate manufacturing processes for top-to-bottom and bottom-to-top vias, thereby reducing parasitic capacitance and resistance by shortening conductive line lengths and eliminating interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional separate manufacturing processes are used for top-to-bottom and bottom-to-top vias, then manufacturing flexibility is maintained, but device complexity and parasitic capacitance increase
Solution Approach 1:
The patent merges the separate manufacturing processes for top-to-bottom and bottom-to-top vias into a single unified self-aligned interconnect structure fabrication process. This is achieved by forming both types of vias simultaneously using the same manufacturing flow, eliminating the need for separate processing steps and reducing overall device complexity while maintaining manufacturing flexibility
2Reliability
If conventional interconnect structures with multiple interfaces are used, then connection flexibility is maintained, but resistance increases
Solution Approach 1:
The patent extracts and eliminates unnecessary interfaces between conductive lines and vias by implementing a self-aligned interconnect structure where conductive lines directly connect to contact plugs without intermediate via interfaces. This reduction in interfaces lowers resistance and associated power consumption while maintaining reliable signal transfer
3Area of stationary object
If longer conductive lines are used in interconnect structures, then connection coverage is improved, but switching speed decreases
Solution Approach 1:
The patent transitions from planar conductive line connections to three-dimensional self-aligned vertical interconnect structures. By stacking contact plugs and conductive lines in multiple layers with precise vertical alignment, the structure achieves extended connection coverage across larger areas while maintaining short current paths and high switching speeds through the vertical dimension
Data Source
AI summary
A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.