Through-Substrate Interconnect Layout for Flexible TSV Routing
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Solution Overview
Problem
Conventional processes for forming through-substrate interconnects in semiconductor dies, such as via-first and via-last processes, face drawbacks including inadequate accommodation of chip-select signals, increased manufacturing complexity and cost, and potential damage to electrical contacts during signal routing structure formation.
Innovation Solution
A process that forms through-substrate interconnects subsequent to the first metallization layer, using a TSV module to create conductive links and routing layers, allowing for flexible and cost-effective integration of through-substrate interconnects without damaging existing electrical connections, and enabling selective connection configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If through-substrate interconnects are formed prior to integrating processing (via-first process), then the interconnect structure is established early in manufacturing, but the process complexity and cost increase, and electrical contacts may be damaged during subsequent signal routing structure formation
Solution Approach 1:
The patent applies preliminary action by forming the through-substrate interconnects before completing the signal routing structure formation. Specifically, deep vias are formed and filled with conductive material through the substrate thickness, establishing the interconnect pathway in advance. This allows subsequent metallization layers to be formed without damaging the interconnects, as the interconnects are already protected by the substrate structure.
2Reliability
If through-substrate interconnects are formed after integration processing (via-last process), then existing electrical connections are protected from damage, but the flexibility to accommodate different connection configurations is reduced
Solution Approach 1:
The patent forms the through-substrate interconnects at an intermediate stage - after the substrate is prepared but before the final signal routing structures are completed. This timing allows the interconnects to be established while still permitting adjustments to the signal routing configurations. The deep vias are formed and filled, then subsequent metallization layers can be optimized for specific connection configurations without risking damage to the interconnects.
3Reliability
If deep vias are formed through the substrate to create through-substrate interconnects, then direct electrical pathways are established, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent segments the via formation process into manageable stages. First, deep vias are formed through the substrate using standard photolithography and etching techniques. Then, the vias are filled with conductive material in a separate step. This segmentation allows each step to be optimized independently, reducing overall manufacturing complexity while maintaining the reliability benefits of through-substrate interconnects.
Data Source
AI summary
Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.