Through-Substrate Via Formation for Smooth Sidewalls and Precise Dimensions
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the minimum feature size of integrated circuits due to process limitations, and stacking two-dimensional ICs into three-dimensional ICs has emerged as a potential solution, with through substrate vias being a key component, but existing methods face issues in forming vias with precise dimensions and smooth sidewalls.
Innovation Solution
A method involving cyclic etching and deposition processes, followed by a trimming process, is used to form through substrate vias with improved sidewall smoothness and aspect ratios, using gases like SF6 and fluorocarbon to achieve precise recess profiles and conductive layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form through substrate vias, then the via can be formed to provide electrical contact, but the sidewalls of the via will be rough and the dimensions will be imprecise
Solution Approach 1:
The patent employs cyclic alternating etching and deposition processes where etching steps are periodically followed by deposition steps. This periodic action allows the sidewalls to be repeatedly formed and smoothed, achieving both precise dimensions and smooth surfaces through multiple iterations of the cycle rather than a single continuous process.
Solution Approach 2:
The deposition process is performed as a preliminary action between etching steps to prepare smooth sidewalls before the next etching operation. This preliminary deposition ensures that subsequent etching produces precise dimensions and smooth sidewalls, preventing the formation of rough surfaces that would occur with conventional direct etching methods.
2Length of moving object
If the minimum feature size is reduced to improve processing capabilities, then IC performance improves, but process limitations make it difficult to continue shrinking
Solution Approach 1:
The patent changes the process parameters by introducing cyclic etching and deposition with specific gas compositions and process conditions. This allows precise control of the via formation process at smaller feature sizes, making it feasible to continue shrinking minimum feature size despite conventional process limitations by optimizing the chemical and physical parameters of the manufacturing process.
3Volume of moving object
If through substrate vias are formed to enable 3D IC stacking, then package size is reduced, but the vias require precise dimensions and smooth sidewalls that are difficult to achieve
Solution Approach 1:
The cyclic alternating etching and deposition process repeatedly forms and smooths the via sidewalls, achieving the precise dimensions and smooth surfaces required for 3D IC stacking. This periodic refinement through multiple cycles enables the high manufacturing precision needed for small package sizes while maintaining via quality.
Solution Approach 2:
The deposition process performs preliminary sidewall smoothing before final via formation, ensuring that the via achieves the required precise dimensions and smooth surface quality. This preliminary preparation enables successful 3D stacking with reduced package size by ensuring via quality is met before completing the formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of through substrate vias with enhanced electrical performance and yield, ensuring smooth sidewalls and precise dimensions, facilitating efficient stacking of ICs in 3D configurations.
Implementation Method 1
performing a cyclic etching and deposition processes from the first surface to form a recess corresponding to the opening
Implementation Method 2
performing a cyclic etching and deposition processes from the first surface to form a recess corresponding to the opening
Data Source
AI summary
The present disclosure relates to a method, which includes forming a patterned mask layer having an opening disposed on a first surface of a substrate; performing a cyclic etching and deposition processes from the first surface to form a recess corresponding to the opening and a liner layer disposed thereon; performing a first removal process to remove the liner layer for exposing a portion of the substrate in the recess; and performing a trimming process to remove the portion of the substrate in the recess.