Vertically Extended Through-Substrate Vias for IC Integration
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Solution Overview
Problem
Current methods for increasing integration density in packaged integrated circuits, such as multi-chip modules, face challenges in effectively providing vertical integration through reliable electrical interconnects within semiconductor substrates.
Innovation Solution
The formation of vertically extended through-substrate vias as electrical interconnects within semiconductor substrates, which involves etching an interlayer dielectric layer and the substrate to create a through-substrate via, filling it with a conductive electrode, and forming multi-level metal interconnects to enhance electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically extended through-substrate vias are formed to provide reliable electrical interconnects, then integration density and electrical connection reliability are improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent applies preliminary action by forming the through-substrate via holes and lining them with sidewall insulating layers before forming the conductive electrodes. This sequence ensures proper insulation and structural integrity are established prior to electrical connection formation, resolving the contradiction between reliability and manufacturing complexity.
Solution Approach 2:
The manufacturing process is segmented into distinct stages: via hole formation, sidewall insulation, electrode formation, and interconnect integration. This segmentation allows each step to be optimized independently, improving reliability while managing manufacturing complexity through systematic process breakdown.
2Productivity
If multi-level metal interconnects are formed to enhance electrical coupling, then integration density increases, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent implements multi-level metal interconnects by extending connections in the vertical dimension through through-substrate vias, in addition to horizontal planar interconnects. This dimensional approach increases integration density without requiring proportional increases in planar area, managing the complexity-density tradeoff effectively.
Solution Approach 2:
The interconnect structure employs nesting by placing conductive electrodes within through-substrate vias, which are themselves embedded in the substrate. Multiple interconnect levels are nested vertically, allowing high integration density while organizing complexity in a hierarchical manner.
3Reliability
If through-substrate vias are etched with tapered sidewalls to improve electrode contact, then electrical connection quality improves, but etching precision requirements increase
Solution Approach 1:
The patent utilizes asymmetric tapered sidewalls in the through-substrate vias, where the angle and profile are specifically designed to optimize electrode contact area. This asymmetric geometry improves reliability by enhancing mechanical and electrical contact while the taper provides self-alignment that actually reduces precision requirements compared to vertical walls.
Solution Approach 2:
The etching process parameters are changed to produce controlled tapered profiles rather than vertical walls. By adjusting etching chemistry, temperature, and duration, the via sidewall angle is optimized to balance electrode contact quality with manufacturable precision tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient vertical integration by providing reliable electrical connections through the substrate, increasing integration density and improving the performance of integrated circuit devices.
Implementation Method 1
This interlayer dielectric layer, which extends on a top surface of the semiconductor substrate, is selectively etched in sequence with the semiconductor substrate to thereby define a through-substrate via extending into the semiconductor substrate
Implementation Method 2
conductive paste is screen-printed onto the substrate
Implementation Method 3
fired to form electrically conductive contact pads
Data Source
AI summary
Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.