Through-Substrate Vias via Backside Isolation Trenches
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Solution Overview
Problem
Conventional through-vias in integrated circuits are formed before or after wiring and device formation, which can lead to inefficiencies and area savings issues, particularly in three-dimensional ICs where direct interconnects are needed after circuit formation.
Innovation Solution
Through-substrate-vias are formed from the backside of the wafer after wiring and devices are fabricated on the front surface, using an isolating trench to create an island part for the via, allowing for direct coupling to nodes above and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional through-vias are formed before wiring and device formation, then the via formation process is simplified, but the wiring and device area is reduced due to via occupation
Solution Approach 1:
The patent inverts the conventional sequence by forming through-vias after wiring and device formation. This allows the front surface to be fully utilized for circuit elements first, then vias are formed from the back surface through the substrate to connect to the previously formed front-surface structures, eliminating area occupation conflicts
Solution Approach 2:
The patent transitions from planar via formation (occupying front surface area) to three-dimensional via formation (extending from back surface through substrate). By utilizing the vertical dimension and forming vias from the back surface, the front surface area is preserved for wiring and devices while still achieving electrical interconnection
2Area of stationary object
If conventional through-vias are formed after wiring and device formation, then wiring and device area is maximized, but the via formation becomes more complex requiring etching through existing structures
Solution Approach 1:
Instead of etching vias through existing front-surface structures, the patent inverts the approach by etching from the back surface. This allows via formation to occur after front-surface circuit elements are complete, maximizing area utilization while simplifying the etching process to only penetrate the substrate thickness without navigating complex front-surface topography
3Strength
If thicker substrates are used for via formation, then structural strength is improved, but via length increases causing higher parasitic capacitance
Solution Approach 1:
The patent segments the substrate into functional regions using isolation trenches that divide the substrate into island and main portions. This segmentation allows the via to be formed in a controlled manner through the substrate thickness while the trench provides electrical isolation, enabling the use of adequate substrate thickness for strength without proportionally increasing via length and parasitic capacitance
Solution Approach 2:
The patent changes the geometric parameters of the via structure by forming it within an isolation trench context. The trench dimensions and positioning allow optimization of via length relative to substrate thickness, and the metal fill process can be controlled to create optimized via dimensions that minimize parasitic capacitance while maintaining the necessary structural strength through the substrate
Data Source
AI summary
Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.