Through-Via Array Substrate Layout for Higher Pixel Resolution
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Solution Overview
Problem
Conventional IC designs using multiple types of transistors for display devices result in a larger transistor area, leading to reduced image resolution due to the occupation of a greater area by transistors, which compromises the display's ability to achieve the advantages of both polysilicon and metal oxide transistors simultaneously.
Innovation Solution
An array substrate structure is developed, featuring a polysilicon switching transistor and a metal oxide driving transistor, where the drain region of the polysilicon transistor is electrically connected to the gate electrode of the metal oxide transistor, utilizing different semiconductor materials to optimize the layout and reduce the overall transistor area, thereby enhancing image resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple types of transistors are used for driving a single pixel, then the advantages of both polysilicon and metal oxide transistors are achieved, but the transistor area increases and image resolution decreases
Solution Approach 1:
The patent combines polysilicon and metal oxide transistors into a single integrated structure where the polysilicon transistor serves as a switching element and the metal oxide transistor serves as a driving element. They share common components such as the gate electrode and semiconductor layer, merging their functions while maintaining their individual performance characteristics. This allows the display device to achieve both the high switch-on current of polysilicon transistors and the low switch-off current of metal oxide transistors without proportionally increasing the overall transistor area.
2Reliability
If multiple types of transistors are used for driving a single pixel, then the advantages of both polysilicon and metal oxide transistors are achieved, but the display region area decreases
Solution Approach 1:
The patent merges multiple transistor functions into a compact integrated structure that shares common components. The polysilicon transistor and metal oxide transistor are configured to share the gate electrode and semiconductor layer, reducing the total area required for transistor operations. This allows more of the substrate area to be allocated to the display region, improving the ratio of display area to non-display area.
3Reliability
If transistors occupy greater area, then the advantages of multiple transistor types are achieved, but the image resolution is reduced
Solution Approach 1:
The patent combines multiple transistor types into a single integrated structure that reduces the total area occupied by transistors. By sharing common components such as the gate electrode and semiconductor layer between the polysilicon and metal oxide transistors, the design minimizes the space required for transistor operations. This area reduction directly improves the pixel density and image resolution of the display device.
Data Source
AI summary
An array substrate structure is provided, which includes a substrate with a first surface and a second surface opposite to the first surface. A first TFT is on the first surface of the substrate, and a second TFT is on the second surface of the substrate. A through via passes through the substrate, and the first TFT is electrically connected to the second TFT through the through via.