Through-Via Backside Planarization for Reliable Semiconductor Wiring
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Solution Overview
Problem
Existing semiconductor devices face challenges in ensuring reliable connections between metal wirings in the Back End of Line (BEOL) and active regions due to defects like leakage current, which occur in non-planarized regions around conductive through-vias.
Innovation Solution
A semiconductor device structure is developed with a conductive through-via penetrating through the semiconductor substrate, featuring a planarized insulating layer on the non-planarized surface around the conductive through-via, allowing for a reliable backside metal connection and preventing defects such as leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conductive through-via is formed to penetrate through the semiconductor substrate for backside wiring connection, then wiring connectivity is improved, but leakage current and connection reliability deteriorate due to non-planarized surfaces around the through-via
Solution Approach 1:
The patent applies local quality by providing a planarized insulating layer specifically at the location of the conductive through-via on the backside surface, while other regions may remain non-planarized. This localized planarization ensures reliable electrical connection and prevents leakage current at the critical via region without requiring complete planarization of the entire backside surface, thus resolving the contradiction between connectivity and reliability.
Solution Approach 2:
The planarized insulating layer acts as an intermediary element between the conductive through-via and the backside metal wiring. This intermediate layer provides a planar interface that ensures uniform electrical contact, prevents direct contact between metal and non-planar substrate surfaces that could cause leakage, and maintains connection reliability while preserving the through-via connectivity function.
2Reliability
If the backside surface is planarized to prevent leakage current, then connection reliability is improved, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent implements selective planarization only in the regions where conductive through-vias are located, rather than planarizing the entire backside surface. This localized approach maintains connection reliability at critical points while significantly reducing manufacturing complexity compared to global planarization, as it requires fewer processing steps and less material removal.
Solution Approach 2:
The patent applies partial action by performing planarization only to the extent necessary - specifically, creating planarized surfaces at via locations sufficient for reliable electrical contact, rather than achieving complete planarization of the entire backside surface. This partial planarization provides the necessary reliability improvement without the excessive manufacturing complexity of full surface planarization.
Data Source
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AI summary
A semiconductor device includes: a device structure including a first semiconductor substrate and having an active pattern extending in first direction, a conductive through-via electrically connected to a front wiring layer and penetrating through the first semiconductor substrate, wherein the first semiconductor substrate has a non-planarized lower surface in which a peripheral region around the conductive through-via curves downward, a first bonding structure having a planarized insulating layer disposed on the second surface of the first semiconductor substrate and having a planarized upper surface.