Through-Via Backside Routing for Source/Drain Interconnect Congestion
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Solution Overview
Problem
The challenge of routing signal wires and power wires at the frontside of semiconductor integrated circuits (ICs) becomes increasingly difficult as they scale down, leading to increased resistance and reduced power efficiency due to limited space for interconnects.
Innovation Solution
Implementing through vias that connect source/drain regions on the frontside of ICs to power and signal lines on the backside, allowing for improved frontside signal routing flexibility and reduced resistance by utilizing power vias and signal vias to deliver power and signals from the backside of the IC device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal wires and power wires are routed at the frontside of ICs, then connectivity is achieved, but resistance increases and power efficiency decreases due to limited space
Solution Approach 1:
The patent introduces through vias that extend vertically through multiple interlayer dielectric layers, transitioning the routing from a two-dimensional frontside plane to a three-dimensional structure. This allows power and signal delivery from the backside of the device, effectively adding a vertical dimension to the interconnect architecture and reducing the congestion on the frontside.
Solution Approach 2:
Instead of routing all power and signal wires through the frontside of the IC, the patent inverts the approach by delivering power and signals from the backside through through vias. This reversal of the conventional routing direction alleviates the frontside routing congestion and reduces resistance.
2Adaptability or versatility
If more interconnect space is allocated on the frontside, then routing flexibility improves, but device area increases
Solution Approach 1:
The patent resolves this contradiction by moving part of the routing functionality to the vertical dimension through through vias. This allows the frontside to be used more efficiently for critical signal routing while power delivery is handled through the vertical structure, effectively increasing routing flexibility without proportionally increasing the device footprint.
3Productivity
If geometry size is scaled down to increase functional density, then production efficiency improves, but routing complexity increases
Solution Approach 1:
As devices are scaled down, the patent's through via structure becomes increasingly valuable by providing a vertical routing path that bypasses the congested horizontal routing layers. This dimensional transition helps manage routing complexity in scaled-down devices by separating power delivery functions from signal routing in the horizontal plane.
Data Source
AI summary
A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.