Through-Via Barrier Wall Layout for Wiring Reliability

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Solution Overview

Problem

As semiconductor devices become miniaturized, large-capacity, and highly integrated, the reliability of metal wires or through vias deteriorates due to errors in manufacturing processes.

Innovation Solution

A semiconductor device is designed with a through via penetrating the substrate and insulating layers, accompanied by a protective barrier wall pattern within the insulating layer and a wiring structure including via and wiring portions, to enhance electrical connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor devices are miniaturized and highly integrated, then device capacity and integration are improved, but reliability of metal wires and through vias deteriorates due to manufacturing errors

Engineering Contradiction:
Improvedevice capacity and integrationVSAvoidreliability of metal wires and through vias
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

A protective barrier wall pattern is introduced as an intermediary structure between the through via and the wiring layer. This barrier wall pattern prevents direct contact and potential contamination between the via fill material and the wiring material, thereby improving reliability without affecting the miniaturization and integration benefits

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protective barrier wall pattern is formed in advance before the wiring layer is deposited. This pre-formed barrier provides protection against manufacturing errors and material contamination from the outset, cushioning the structure against potential reliability issues that could arise during subsequent processing steps

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If protective barrier wall pattern is added to improve reliability, then manufacturing complexity increases

Engineering Contradiction:
Improvereliability of through viaVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective barrier wall pattern formation process is merged with the existing via formation process. The barrier wall pattern is formed using the same etching and deposition steps that are already part of the manufacturing flow, rather than adding completely separate process steps. This integration minimizes the increase in manufacturing complexity while still providing the reliability benefits

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4535412A1Semiconductor device including a through via and a wiring layer
Publication Date: 2025.04.09 SAMSUNG ELECTRONICS CO LTD
  • EP4535412A1 patent drawingFigure 1A
  • EP4535412A1 patent drawingFigure 1B
  • EP4535412A1 patent drawingFigure 1C

AI summary

A semiconductor device includes a semiconductor substrate, a first insulating layer disposed on a first surface of the semiconductor substrate, a through via passing through both the semiconductor substrate and the first insulating layer, a protective barrier wall pattern disposed within the first insulating layer and on a sidewall of the through via, a first wiring structure disposed within the first insulating layer and including a first via portion and a first wiring portion, and a second insulating layer disposed on an upper surface of the first insulating layer and at least partially covering an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern.