Through-Via Bridge Chip Interconnect for Tighter Pitch Packaging
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Solution Overview
Problem
Conventional chip integration techniques face challenges such as poor scalability, high parasitics, and thermal stress in solder connections, and difficulties in implementing copper-to-copper (Cu-Cu) bonding due to planarity and contamination issues, especially when integrating a bridge chip into a laminate package.
Innovation Solution
The use of a bridge chip with through vias that eliminate external connections by forming conductive vias in the bridge chip, which directly contact the metal lines of the chips, allowing for tighter pitches and high-bandwidth connectivity without the need for solder or Cu-Cu interface connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If solder connections are used to attach the bridge chip to the laminate package, then the chips can be connected with relatively low power losses, but the pitch is large and scalability to smaller chip dimensions is difficult
Solution Approach 1:
The patent transitions from external 2D solder connections to internal 3D through-via connections. The conductive vias extend vertically through the bridge chip substrate, enabling direct electrical contact between chips in the Z-dimension while reducing the lateral pitch requirement. This dimensional transition allows tighter spacing between connection points.
Solution Approach 2:
The bridge chip itself serves as an intermediary structure that eliminates the need for external solder connections. The conductive vias within the bridge chip substrate act as intermediaries to establish direct electrical pathways between the first and second chips, replacing the traditional solder joint mediator.
2Length of moving object
If copper-to-copper chip connections are implemented to achieve tighter pitches, then the pitch can be reduced, but the planarity requirements and contamination issues make implementation difficult
Solution Approach 1:
The bridge chip substrate with integrated conductive vias serves as an intermediary that eliminates the need for direct Cu-to-Cu bonding. Instead of requiring two copper surfaces to bond directly (which demands strict planarity and contamination control), the through-via structure provides a buffered connection pathway that is more tolerant of manufacturing variations.
Solution Approach 2:
The connection path is segmented into multiple discrete components: the via hole through the substrate, the conductive material filling the via, and the contact pads on each chip. This segmentation allows each component to be optimized and controlled independently, reducing the cumulative manufacturing difficulty compared to direct Cu-to-Cu bonding.
3Adaptability or versatility
If a recessed bridge chip design is used in the laminate package, then the integration can be achieved, but a customized recess-bearing laminate is needed which is difficult and costly to fabricate
Solution Approach 1:
The patent extracts the complexity from the laminate package by eliminating the need for recesses. The bridge chip is designed to sit flush or protrude slightly from the laminate surface, removing the requirement for customized recess-bearing laminates and their associated fabrication challenges.
Solution Approach 2:
Instead of modifying the laminate package to accommodate the bridge chip (creating recesses in the laminate), the approach is inverted: the bridge chip is designed with through-vias that enable direct connection without requiring any modification to the laminate structure. The complexity is shifted from the laminate to the bridge chip fabrication.
Data Source
AI summary
Techniques for interconnecting chips using a bridge chip having through vias is provided. In one aspect, a structure includes: a bridge chip attached to at least a first chip and a second chip, wherein the bridge chip has at least one conductive through via connecting the bridge chip to one of the first chip and the second chip. The bridge chip can include a wiring layer having metal lines present between a first capping layer and a second capping layer, and the at least one conductive through via can directly contact at least a sidewall of at least one of the metal lines. A method of integrating chips using the present bridge chip is also provided.