Through Via Connection Testing via Buffer Circuits
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Solution Overview
Problem
Existing semiconductor devices with through vias face challenges in detecting failures before stacking, as they require multiple chips to check characteristics, leading to difficulties in identifying issues with each through via prior to assembly.
Innovation Solution
A semiconductor device configuration that includes a through via penetrating the substrate, a first and second buffer circuit, and a connecting wiring portion on the chip inner end face, allowing for the connection of paths to check the connection state from the through via to the chip line using only the own chip, enabling detection of abnormalities due to expansion or contraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a plurality of semiconductor chips is used to check through via characteristics, then the characteristics of through vias can be checked, but it becomes difficult to check failures prior to stacking and increases device complexity
Solution Approach 1:
The invention divides the testing function into two stages: first testing the through via connection state within a single chip using the connecting wiring portion and buffer circuits, then proceeding to chip stacking only if the test passes. This segmentation allows failure detection at the component level rather than requiring multiple chips to be stacked for testing.
Solution Approach 2:
The invention performs the through via connection test before chip stacking by providing test paths that connect to the through via within the same chip. This preliminary testing action identifies failures early in the manufacturing process, preventing defective chips from being stacked and wasted.
2Productivity
If through via connection testing is performed before stacking, then manufacturing yield improves, but additional wiring and circuits increase device complexity
Solution Approach 1:
The connecting wiring portion serves dual functions: it connects the buffer circuits to the through via for testing purposes, and it also serves as part of the signal transmission path during normal operation. This multi-functionality allows testing capability to be added without proportionally increasing device complexity.
Solution Approach 2:
The connecting wiring portion acts as an intermediary structure that enables testing by providing a controllable connection point between the buffer circuits and the through via. This intermediary allows test signals to be applied and measured without requiring external testing equipment or chip stacking.
3Reliability
If the connecting wiring portion is formed on the chip inner end face, then single-chip testing becomes possible, but manufacturing precision requirements increase
Solution Approach 1:
The invention forms the connecting wiring portion on the end face of the through via, which is a different spatial dimension from the traditional planar wiring layout. This dimensional change allows the wiring to naturally follow the three-dimensional structure of the through via, reducing alignment complexity and manufacturing precision requirements despite enabling precise connection state detection.
Data Source
AI summary
A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.