Through Via Capacitance Comparison for Semiconductor Yield
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Solution Overview
Problem
The formation of through vias in semiconductor apparatuses is prone to processing errors, leading to decreased manufacturing yield and increased costs due to abnormal metal layer formation, which affects signal transfer and productivity.
Innovation Solution
A semiconductor apparatus equipped with a comparison unit that includes a reference capacitor to assess the capacitance value of through vias, allowing for the determination of normal formation by comparing it with a predetermined capacitance value, thereby preventing unnecessary processes and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through vias are formed in semiconductor chips to enable 3D stacking and improve integration density, then manufacturing complexity and processing error risks increase
Solution Approach 1:
The patent applies preliminary action by forming a protective coating layer on the metal layer before filling the through via. This pre-protection measure prevents oxidation and contamination during subsequent processing steps, thereby reducing processing errors and improving yield while enabling the 3D stacking structure for higher integration density
2Reliability
If metal layers are filled in through via paths to create electrical connections, then signal transfer capability improves, but processing errors such as gaps and voids increase
Solution Approach 1:
The patent forms a protective coating layer on the metal layer surface before completing the via fill process. This preliminary protection prevents oxidation and contamination that could create gaps or voids, ensuring complete and defect-free metal filling while maintaining reliable electrical connectivity
Solution Approach 2:
The protective coating layer acts as an intermediary between the metal layer and the surrounding environment. It prevents direct exposure to oxidizing agents and contaminants, thereby eliminating the formation of gaps and voids that would compromise signal transfer reliability
3Productivity
If abnormal through via formation is detected late in the manufacturing process, then manufacturing yield decreases and additional costs are incurred
Solution Approach 1:
The patent incorporates a test structure with a through via that mirrors the actual via formation process. By testing this reference structure immediately after via formation, the system provides real-time feedback on processing quality, enabling early detection of abnormalities and preventing waste of subsequent processing steps on defective chips
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively identifies normal or abnormal through via formation, enhancing manufacturing productivity and reducing costs by preventing further processing of defective chips and ensuring stable signal transfer.
Implementation Method 1
a comparison unit (202) including a reference capacitor (203), and configured to compare a capacitance value of the through via (201) and a capacitance value of the reference capacitor (203)
Data Source
AI summary
A semiconductor apparatus includes a through via and a comparison unit. The through via is electrically connected with another chip. The comparison unit includes a reference capacitor, and compares a capacitance value of the through via and a capacitance value of the reference capacitor in response to a test start signal and a reset signal and generates a comparison result.