Through-Via Capping Pad Structure for Lower Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in reducing resistance between through-vias and via connection pads, which affects the high capacity and bandwidth required for processing increasing data volumes.
Innovation Solution
The implementation of a capping-type via connection pad configuration, featuring a first capping-type via connection pad on the upper surface of the through-via and a second capping-type via connection pad with a greater width, surrounding the first, to reduce resistance between the through-via and the via connection pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a through-via is used as an electrode, then the capacity and bandwidth of the semiconductor device are improved, but the resistance between the through-via and the via connection pad increases
Solution Approach 1:
The via connection pad is designed with a capping-type structure that extends laterally over the through-via, transitioning from a simple planar contact to a three-dimensional configuration. This dimensional change increases the contact area between the via connection pad and the through-via, thereby reducing resistance while maintaining the high capacity and bandwidth benefits of the through-via electrode structure
Solution Approach 2:
The via connection pad is divided into multiple segments: a first via connection pad at a first level and a second via connection pad at a second level, with the second pad having a greater width than the first. This segmentation creates a stepped capping structure that progressively increases the contact area with the through-via, effectively reducing resistance while maintaining structural integrity
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; an integrated circuit layer disposed on the semiconductor substrate; a first metal wiring layer to an n-th metal wiring layer sequentially disposed on the semiconductor substrate and the integrated circuit layer, wherein n is a positive integer; a plurality of wiring vias connecting the first to n-th metal wiring layers to each other, and a through-via extending in a vertical direction from a via connection pad, which is any one of the first metal wiring layer to the n-th metal wiring layer, toward the semiconductor substrate and penetrating the semiconductor substrate, wherein the via connection pad is a capping-type via connection pad formed on an upper surface of the through-via.