Through-Via Capping Pad Structure for Lower Interconnect Resistance
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Solution Overview
Problem
Semiconductor devices with through-vias face challenges in reducing resistance between the through-via and the via connection pad, limiting their high-capacity and high-bandwidth performance.
Innovation Solution
The semiconductor device incorporates a capping-type via connection pad with a first and second capping-type via connection pad, where the second capping-type via connection pad has a greater width than the first, formed on the upper surface of the through-via, reducing resistance by 20% to 60% compared to traditional line-shaped or rod-shaped pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a through-via is used as an electrode to increase data processing capacity and bandwidth, then the high-capacity and high-bandwidth performance is improved, but the resistance between the through-via and the via connection pad increases
Solution Approach 1:
The via connection pad is transformed from a traditional line-shaped or rod-shaped structure to a capping-type structure that covers the upper surface of the through-via. This dimensional change from linear/point contact to surface coverage significantly increases the contact area between the pad and the through-via, thereby reducing resistance while maintaining the high-capacity and high-bandwidth performance enabled by the through-via electrode structure
2Device complexity
If a traditional line-shaped or rod-shaped via connection pad is used, then the device structure is simple, but the resistance between the through-via and the via connection pad is high
Solution Approach 1:
The via connection pad is transformed from a traditional line-shaped or rod-shaped structure to a capping-type structure that covers the upper surface of the through-via. This dimensional change from linear/point contact to surface coverage significantly increases the contact area between the pad and the through-via, thereby reducing resistance while maintaining the high-capacity and high-bandwidth performance enabled by the through-via electrode structure
Data Source
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AI summary
A semiconductor device includes: a semiconductor substrate; an integrated circuit layer disposed on the semiconductor substrate; a first metal wiring layer to an n-th metal wiring layer sequentially disposed on the semiconductor substrate and the integrated circuit layer, wherein n is a positive integer; a plurality of wiring vias connecting the first to n-th metal wiring layers to each other; and a through-via extending in a vertical direction from a via connection pad, which is any one of the first metal wiring layer to the n-th metal wiring layer, toward the semiconductor substrate and penetrating the semiconductor substrate, wherein the via connection pad is a capping-type via connection pad formed on an upper surface of the through-via.