Through-Via Cell Placement Using Soft Keep-Out Zones
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Solution Overview
Problem
As semiconductor devices demand higher integration, existing methods struggle to efficiently manage the placement of standard cells around through-vias while maintaining performance and avoiding defects, leading to spatial overhead and potential damage from stress caused by these vias.
Innovation Solution
The method involves determining a keep-out zone around through-vias based on saturated current variation rates and placing standard cells within this zone, setting timing margins according to the distance from the vias, and using a cell library to optimize cell placement and routing, thereby reducing spatial overhead and minimizing stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If standard cells are placed close to through-vias to increase integration density, then spatial overhead is reduced, but stress and current variation affect device reliability
Solution Approach 1:
The patent applies local quality by creating a non-uniform placement strategy where cells are selectively placed in keep-out zones around through-vias based on their specific characteristics. The keep-out zone distance is determined by saturated current variation rates, allowing cells to be placed closer to through-vias where current variation is acceptable while maintaining larger distances where variation is high, thus optimizing both density and reliability locally
Solution Approach 2:
The patent changes the parameter of cell placement distance based on saturated current variation rates. By calculating and analyzing current variation as a function of distance from through-vias, the system dynamically determines keep-out zone distances rather than using fixed rules, allowing optimization of both spatial utilization and device reliability through parameter-based decision making
2Productivity
If through-vias are used for high integration but cells are placed too close, then spatial efficiency improves, but stress causes defects
Solution Approach 1:
The patent applies preliminary action by pre-calculating saturated current variation rates and determining keep-out zone distances before cell placement. The system analyzes the relationship between distance from through-vias and current variation, establishes safe placement zones in advance, and then uses these pre-determined zones to guide cell placement, preventing stress-induced defects before they occur
Solution Approach 2:
The patent introduces saturated current variation rate analysis as an intermediary between through-via placement and cell placement decisions. This intermediary parameter serves as a mediator that quantifies the harmful effect of through-vias and translates it into actionable keep-out zone distances, enabling systematic management of stress-induced defect risks
3Reliability
If keep-out zones are enlarged to protect cells from through-via stress, then device reliability improves, but spatial overhead increases
Solution Approach 1:
The patent dynamically adjusts keep-out zone sizes based on saturated current variation rates rather than using fixed conservative distances. By changing the parameter of keep-out zone distance according to actual current variation measurements, the system minimizes unnecessary spatial overhead while maintaining adequate protection for cells from through-via stress
Data Source
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AI summary
An example embodiment provides a design method of an integrated circuit, including: placing a through-via (112); determining a keep-out zone (114) around the through-via (112) based on a saturated current variation rate according to a distance from the through-via (112); placing standard cells; determining a cell placed within the keep-out zone (114) among the cells; and setting a timing margin based on the distance from the through-via (112) to the cell.