Through-Substrate Via Interconnect Barrier Against Contamination
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in preventing contamination from entering interconnect structures during through substrate via formation, which can damage metallization patterns and dielectric layers, leading to reduced device reliability and performance.
Innovation Solution
Incorporating a passivation layer, such as silicon nitride or undoped silicate glass, between the through substrate via and the interconnect or redistribution structure to block contaminants like moisture and chemicals, thereby preventing damage to the metallization patterns and dielectric layers during the formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through substrate via formation is performed without a passivation layer, then manufacturing process is simpler and faster, but contaminants enter the interconnect structure causing damage to metallization patterns and dielectric layers
Solution Approach 1:
A passivation layer is introduced as an intermediary barrier between the through substrate via formation process and the interconnect structure. This layer selectively blocks contaminants (moisture, chemicals) from reaching the metallization patterns and dielectric layers while allowing the via formation process to proceed. The passivation layer serves as a protective mediator that resolves the contradiction between maintaining simple processing and ensuring device reliability.
Solution Approach 2:
The passivation layer is formed in advance before the through substrate via formation process. This preliminary action prepares the interconnect structure by establishing a protective barrier that prevents contamination during subsequent processing steps. By performing the protection action beforehand, the methodology ensures reliability without requiring complex modifications to the overall manufacturing flow.
2Reliability
If a passivation layer is added to protect interconnect structures, then device reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The passivation layer acts as a straightforward intermediary component that can be integrated into existing manufacturing processes. Rather than requiring complex process changes, it adds a single protective step that blocks contaminants during through via formation, thereby improving reliability while maintaining manufacturing simplicity.
3Productivity
If contaminants are allowed to enter during through via formation, then manufacturing process is faster, but metallization patterns and dielectric layers are damaged
Solution Approach 1:
The passivation layer serves as a protective intermediary that allows the through via formation process to proceed at normal speed without compromising interconnect integrity. It selectively permits the formation process while blocking harmful contaminants, thus maintaining both productivity and manufacturing precision simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passivation layer effectively blocks contaminants, preventing damage to the interconnect layers and enhancing the reliability and performance of semiconductor devices by maintaining the integrity of metallization patterns and dielectric layers.
Implementation Method 1
Incorporating a passivation layer, such as silicon nitride or undoped silicate glass, between the through substrate via and the interconnect or redistribution structure to block contaminants like moisture and chemicals
Data Source
AI summary
An embodiment is a method including forming a first interconnect structure over a first substrate, the first interconnect structure comprising dielectric layers and metallization patterns therein, patterning the first interconnect structure to form a first opening, coating the first opening with a barrier layer, etching a second opening through the barrier layer and the exposed portion of the first substrate, depositing a liner in the first opening and the second opening, filling the first opening and the second opening with a conductive material, and thinning the first substrate to expose a portion of the conductive material in the second opening, the conductive material extending through the first interconnect structure and the first substrate forming a through substrate via.