Through-Via Structure With Dielectric Cap to Prevent Copper Popping
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher integration density and smaller form factors for electronic devices, as existing packaging techniques are limited in connecting electrical circuits in stacked semiconductor dies effectively.
Innovation Solution
The implementation of through silicon vias, formed by creating openings in the semiconductor substrate and filling them with conductive materials, along with a liner, barrier, and seed layers, allows for vertical connections and reduces production time and costs by employing a via-first fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging techniques are used to connect stacked semiconductor dies, then the manufacturing process is simpler, but the integration density is lower and form factor is larger
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked die architecture, enabling vertical interconnections through through-silicon vias (TSVs). This dimensional change allows multiple semiconductor dies to be stacked vertically, dramatically increasing integration density by utilizing the third dimension (height) rather than only expanding in the planar direction.
Solution Approach 2:
The via-first fabrication process performs through-silicon via formation and conductive material filling before die stacking. This preliminary action prepares the vertical interconnection channels in advance, enabling efficient electrical connections between stacked dies and reducing overall manufacturing complexity compared to forming vias after stacking.
2Quantity of substance
If minimum feature size is continuously reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuously reducing minimum feature size in the planar direction, the patent utilizes the vertical dimension through TSVs and stacked dies. This approach increases integration density by stacking multiple dies vertically, thereby avoiding the need to further reduce already minimal planar feature sizes and the associated manufacturing precision challenges.
3Reliability
If through silicon vias are formed with multiple layers (liner, barrier, seed), then reliability is improved by preventing copper popping, but manufacturing complexity increases
Solution Approach 1:
The patent applies a multi-layer structure (liner layer, barrier layer, and seed layer) to the through-silicon via walls before filling with conductive material. The liner layer provides mechanical support to prevent copper popping, the barrier layer prevents diffusion, and the seed layer enables electroplating. This beforehand cushioning approach ensures reliability by preventing potential failure modes before they occur during subsequent processing and operation.
Solution Approach 2:
The patent combines multiple protective and functional layers (liner, barrier, and seed layers) into an integrated via structure. These layers are deposited sequentially to form a unified multi-layer coating that simultaneously provides mechanical support, diffusion protection, and electroplating functionality, thereby achieving multiple objectives through a consolidated fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density, smaller form factors, cost-effectiveness, and reduced power consumption by facilitating efficient electrical connections in stacked semiconductor dies, while minimizing reliability issues like copper popping.
Implementation Method 1
a seed layer is formed over the barrier layer. A dielectric layer is formed over the seed layer. A conductive material is deposited over the dielectric layer
Data Source
AI summary
A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.