Through-Via Display Layout for Smaller Non-Display Borders
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Solution Overview
Problem
Display devices face challenges in reducing the size due to the area constraints imposed by non-display regions, which limits their miniaturization and efficiency, especially in applications like head-mounted displays for virtual and augmented reality.
Innovation Solution
The integration of a semiconductor chip on the lower surface of a substrate with a thin-film substrate and through-vias that electrically connect them, allowing for a reduced non-display region size and enabling a more compact display device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the non-display region is reduced to minimize device size, then the area constraint is improved, but the electrical connection between components becomes more difficult to implement
Solution Approach 1:
The patent transitions electrical connections from a planar layout to a three-dimensional stacked architecture. Through-vias penetrate the substrate vertically to connect the semiconductor chip on the lower surface with the thin-film substrate on the upper surface, enabling electrical connectivity without requiring additional horizontal space in the non-display region.
Solution Approach 2:
The patent implements a nested configuration where the semiconductor chip is positioned on the lower surface of the substrate, through-vias pass through the substrate body, and the thin-film substrate is positioned on the upper surface. This nested arrangement through the substrate thickness enables compact integration of multiple functional layers with efficient electrical interconnection.
2Volume of moving object
If components are integrated on the lower surface of the substrate, then the device miniaturization is improved, but the structural complexity increases
Solution Approach 1:
The patent divides the display device into distinct functional segments: a light-emitting element layer on the upper surface of the substrate, a semiconductor chip on the lower surface, and connecting through-vias. This segmentation allows each component to be optimized independently and simplifies the manufacturing process by enabling separate fabrication and assembly of individual modules.
Solution Approach 2:
The patent utilizes the vertical dimension (z-axis) through the substrate thickness to accommodate multiple functional components. By positioning the semiconductor chip on the lower surface and the thin-film substrate on the upper surface with through-vias connecting them, the design effectively uses the substrate thickness as a useful dimension for component integration, reducing the horizontal footprint.
Data Source
AI summary
A display device is provided. The display device includes a substrate including a display region and a non-display region adjacent to the display region in a first horizontal direction, a light-emitting element layer on an upper surface of the substrate in the display region, a thin-film substrate connected to the upper surface of the substrate in the non-display region, a first semiconductor chip on a lower surface of the substrate, at least a portion of the first semiconductor chip overlapping with the thin-film substrate in a vertical direction, and a first through-via in the non-display region, the first through-via extending through the substrate in the vertical direction, the first through-via electrically connecting the thin-film substrate and the first semiconductor chip to each other.