Through-Substrate Via Structure With Dummy Pillars for 3DIC Heat Control

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Solution Overview

Problem

The semiconductor industry faces challenges in manufacturing three-dimensional integrated circuits (3DICs) due to complexities in stacking semiconductor dies and forming efficient interconnects, which affect integration density, speed, and thermal resistance.

Innovation Solution

A manufacturing method involving the formation of through substrate vias, conductive pillars, and dummy conductive pillars is developed, allowing for efficient electrical connections and thermal management by integrating these components into a single-sided semiconductor structure, reducing manufacturing costs and thermal resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional stacking methods are used to form 3DICs, then integration density and speed are improved, but manufacturing complexity and thermal resistance increase

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the interconnection structure into separate components: through substrate vias formed in the semiconductor substrate, and conductive pillars formed in the interconnection structure. This segmentation allows independent formation and optimization of each component, reducing manufacturing complexity while maintaining high integration density.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar 2D interconnections to 3D vertical interconnections by forming through substrate vias that penetrate the semiconductor substrate and conductive pillars that extend vertically in the interconnection structure. This dimensional change enables shorter interconnect paths and higher integration density without increasing manufacturing complexity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If conventional stacking methods are used to form 3DICs, then integration density and speed are improved, but thermal resistance increases

Engineering Contradiction:

Improvesignal speedVSAvoidthermal resistance

Core Design Contradiction:

SpeedVSTemperature

Solution Approach 1:

The patent introduces a via fill material that serves as a thermal intermediary, conducting heat away from the stacked semiconductor dies through the through substrate vias. This thermal pathway reduces thermal resistance while maintaining the high-speed signal transmission benefits of short interconnects.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If through substrate vias and conductive pillars are formed, then thermal resistance is reduced and integration density is enhanced, but manufacturing precision requirements increase

Engineering Contradiction:

Improveintegration densityVSAvoidvia and pillar alignment precision

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent forms through substrate vias in the semiconductor substrate before forming the interconnection structure and conductive pillars. This preliminary action establishes a predefined alignment reference, reducing the precision requirements for subsequent pillar formation and improving overall manufacturing feasibility.

Inventive Principle:

Principle #10Preliminary action

4Ease of manufacture

If conventional stacking processes are used, then 3DICs can be manufactured, but additional carrier attachment and flipping processes are required, increasing manufacturing cost

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidmanufacturing cost

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent inverts the conventional stacking approach by forming through substrate vias that extend through the substrate and make direct contact with bonding pads on the semiconductor die. This inversion eliminates the need for carrier attachment and flipping processes, simplifying manufacturing and reducing costs while maintaining high integration density.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11855021B2Semiconductor structure with through substrate vias and manufacturing method thereof

Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.