Through-Via ESL Recess for Continuous Barrier Layer Formation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In semiconductor devices, ensuring the quality of electrical connections between transistors and conductive layers is challenging due to the complexity of forming high-quality conductive layers through vias.

Innovation Solution

The semiconductor device incorporates an etching stop layer (ESL) structure with a recessed first depth ranging from 1 nm to 7 nm, covered by a continuous barrier layer, which enhances the yield and reliability of the electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a through via is filled with metal material to form a conductive layer, then electrical connection between transistors is achieved, but the forming quality and reliability of the conductive layer become challenging to ensure

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidconductive layer forming quality

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

A recess is formed in the etching stop layer before depositing the barrier layer and conductive layer. This preliminary structural preparation ensures that the barrier layer can be continuously formed without defects, thereby guaranteeing the quality and reliability of the subsequent conductive layer filling process

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

An etching stop layer with a recess structure is introduced as an intermediary layer between the underlying structure and the barrier layer. This intermediary structure facilitates the continuous formation of the barrier layer and improves the overall manufacturing precision of the conductive layer

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the barrier layer is formed to cover the through via, then protection of the conductive layer is achieved, but discontinuity or damage to the barrier layer may occur

Engineering Contradiction:

Improvebarrier layer continuityVSAvoidbarrier layer damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A recess is formed in the etching stop layer before depositing the barrier layer. This preliminary action creates a favorable geometric configuration that enables the barrier layer to be continuously deposited without interruption, preventing defects and ensuring complete coverage

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The recess structure in the etching stop layer acts as a cushioning feature that accommodates the barrier layer deposition process, preventing potential damage or discontinuity by providing a preparatory structural buffer

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250069989A1Semiconductor device and manufacturing method thereof

Publication Date: 2025.02.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.