Through-Via Etching Stopper Structure to Prevent Metal Fill Defects

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Solution Overview

Problem

The prior art semiconductor devices experience metal embedding defects due to bowing of the etched portion and poor etching control when forming through-vias, which affects the electrical connectivity between stacked semiconductor substrates.

Innovation Solution

A semiconductor device with a stacked structure is developed, featuring a rewiring layer, an etching stopper layer on the bonding surface, a die bonded via the etching stopper layer, and an isolation film covering the die and the etching stopper layer. This configuration prevents metal embedding defects by ensuring precise etching and electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional etching is performed after etching up to the etching stopper layer to form through-vias, then electrical connectivity between stacked devices is achieved, but the etched portion bulges and becomes bowing, causing metal embedding defects

Engineering Contradiction:
Improveelectrical connectivityVSAvoidetching precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the etching stopper layer before performing the additional etching. This protective film prevents the etching gas from directly attacking the etching stopper layer, thereby preventing bowing of the etched portion while still allowing the etching to proceed to achieve electrical connectivity through the through-vias.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If etching is performed to penetrate the isolation film and etching stopper layer to form through-vias, then electrical connection between substrate and die is achieved, but metal embedding defects occur in the bow-shaped portion

Engineering Contradiction:
Improveelectrical connectionVSAvoidvia formation process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the etching stopper layer before performing the additional etching. This protective film prevents the etching gas from directly attacking the etching stopper layer, thereby preventing bowing of the etched portion while still allowing the etching to proceed to achieve electrical connectivity through the through-vias.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the etching stopper layer is etched away completely to form through-vias, then electrical connectivity is achieved, but the etching process becomes difficult to control and causes bowing

Engineering Contradiction:
Improveelectrical connectivityVSAvoidetching control
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the etching stopper layer before performing the additional etching. This protective film prevents the etching gas from directly attacking the etching stopper layer, thereby preventing bowing of the etched portion while still allowing the etching to proceed to achieve electrical connectivity through the through-vias.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively prevents metal embedding defects and ensures reliable electrical connectivity between the substrate and the die, enhancing the manufacturing process and device performance.

Implementation Method 1

an etching rate when etching the etching stopper layer with a predetermined etching gas may be lower than an etching rate when etching the isolation film with the etching gas

Methodology Applied
Scientific EffectEtching rate difference:

Data Source

PatentUS20250132237A1Semiconductor device and method for manufacturing semiconductor device
Publication Date: 2025.04.24 SONY SEMICON SOLUTIONS CORP
  • US20250132237A1 patent drawing
  • US20250132237A1 patent drawing
  • US20250132237A1 patent drawing

AI summary

To prevent a metal embedding defect in a semiconductor device in which a through-via is formed. The semiconductor device includes a substrate, an etching stopper layer, a die, and an isolation film. In the semiconductor device, a rewiring layer is formed on the substrate. The etching stopper layer is formed on a bonding surface of the rewiring layer. The die is bonded to a partial region of the bonding surface via the etching stopper layer. The isolation film covers the die and the etching stopper layer.