Through-Via and Extension Pad Layout for Stacked Semiconductor Packages
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Solution Overview
Problem
The integration of multiple semiconductor devices in wafer-level packaging poses challenges for miniaturization, higher speed, and reduced transmission and insertion losses, requiring innovative packaging and assembling techniques to meet the demands of modern electronic devices.
Innovation Solution
A semiconductor package manufacturing process involving a carrier with de-bonding layers, encapsulating materials, seed material layers, high-modulus dielectric layers, and redistribution structures to facilitate electrical connections and mechanical stress dissipation, allowing for efficient integration and separation of semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor devices are integrated in wafer-level packaging, then device integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the manufacturing process into distinct segments: forming through vias in the first substrate, creating redistribution layers, bonding the second substrate, and then separating individual packages. This segmentation allows complex multi-device integration to be achieved through manageable, repeatable steps, resolving the contradiction between high integration and manufacturing complexity
Solution Approach 2:
The patent transitions from planar wafer-level processing to three-dimensional stacked packaging by forming vertical through vias and stacking substrates. This dimensional change enables multiple devices to be integrated in the vertical dimension rather than requiring increased lateral wafer area, thereby improving integration without proportionally increasing manufacturing complexity
2Length of moving object
If miniaturization is pursued, then device size is reduced, but transmission loss increases
Solution Approach 1:
The patent moves electrical connections from lateral routing on a single wafer plane to vertical routing through stacked substrates. This dimensional transition shortens the transmission path length despite reduced device footprint, thereby maintaining signal integrity while achieving miniaturization and reducing transmission loss
Solution Approach 2:
The patent introduces redistribution layers as intermediary conductive structures that efficiently route signals between through vias and device contact pads. These intermediary layers optimize signal paths and reduce transmission loss by providing low-impedance, controlled-length connection paths in the miniaturized stacked architecture
3Reliability
If through vias and stacked redistribution layers are implemented, then electrical connection is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming through vias and redistribution layers in the first substrate before bonding to the second substrate. This preliminary preparation ensures that electrical connections are established in advance, improving reliability while allowing the bonding process to proceed without additional complexity
Solution Approach 2:
The patent merges multiple functions into integrated structures: through vias serve both as mechanical anchors and electrical conduits, while redistribution layers simultaneously provide signal routing and impedance control. This functional merging improves electrical connection reliability without proportionally increasing manufacturing process complexity
Data Source
AI summary
A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.