Through-Package Via Layout for High-Density Fan-Out Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging efficiency as traditional methods struggle to effectively integrate multiple semiconductor devices in a compact form factor, leading to a need for innovative packaging techniques that can reduce physical size while maintaining performance and reliability.
Innovation Solution
The method involves forming three-dimensional integrated fan-out (InFO) package-on-package (PoP) devices using a carrier substrate with a release layer, patterned layers, and seed layers to create through vias that allow for the stacking and electrical connection of multiple semiconductor wafers, enabling efficient redistribution of electrical connections and encapsulation, thereby reducing the physical size of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional packaging methods are used, then manufacturing simplicity is maintained, but integration density and miniaturization are limited
Solution Approach 1:
The patent transitions from traditional two-dimensional planar packaging to three-dimensional stacked packaging by forming vertical through-package vias that penetrate the entire package thickness. Multiple semiconductor dies are stacked vertically and interconnected through these vias, enabling higher integration density by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The package is divided into multiple discrete semiconductor dies stacked vertically, with each die being separately fabricated and then interconnected through the formed vias. This segmentation allows independent optimization of each die while achieving high integration density through vertical stacking.
2Volume of moving object
If multiple semiconductor wafers are stacked to reduce form factor, then physical size is reduced, but manufacturing complexity increases
Solution Approach 1:
The through-package vias are formed before the semiconductor dies are stacked and attached. The vias extend through the entire package structure including future die locations, allowing subsequent dies to be attached and interconnected through pre-formed pathways. This preliminary via formation simplifies the overall manufacturing process by establishing interconnection routes before component assembly.
Solution Approach 2:
A carrier substrate is used as an intermediary structure to support the formation of vias and subsequent die attachment. The carrier provides a stable platform for via formation and die stacking, and is removed after bonding, leaving the finished stacked package. This intermediary facilitates complex manufacturing steps while maintaining process control.
3Manufacturing precision
If through package vias are formed to enable vertical interconnection, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The via formation process is segmented into distinct stages: initial via opening formation, seed layer deposition, and conductive material filling. Each stage is optimized independently, allowing precise control of via dimensions and conductive material placement while managing manufacturing complexity through process decomposition.
Data Source
AI summary
A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.