Through-Via Interposer Package Layout for Low-Warpage PoP Stacking
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges in minimizing warpage and reducing z-height in package-on-package arrangements, which are essential for smaller electronic devices.
Innovation Solution
The implementation of a through-via interposer with an embedded die package, featuring conductive vias that electrically connect the front and back sides of the package, allowing for stacked arrangements with minimized warpage and reduced z-height, achieved through the use of a mold compound and conductive pathways that match the thermal expansion characteristics of the die material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional IC packages are used in package-on-package arrangements, then electrical connectivity between layers is achieved, but warpage increases and z-height increases
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the first and second IC packages. The interposer provides through-via conductive pathways that enable electrical connectivity while its rigid structure serves as a stable mounting platform, preventing warpage from propagating through the package-on-package assembly. The interposer acts as a mediator that decouples the thermal and mechanical stresses between the two packages.
Solution Approach 2:
The patent transitions from traditional lateral/package-side connectivity to vertical through-via connectivity by drilling conductive pathways through the interposer substrate in the vertical dimension. This dimensional change allows electrical signals to pass through the interposer from one package to another, enabling compact z-height stacking while maintaining reliable electrical connections without requiring large lateral footprint expansions.
2Reliability
If traditional IC packages are used in package-on-package arrangements, then electrical connectivity is achieved, but z-height increases
Solution Approach 1:
The first IC package, interposer, and second IC package are arranged in a nested vertical stacking configuration where the second package is mounted on top of the interposer which itself is mounted on the first package. This nesting approach minimizes the overall z-height by efficiently utilizing vertical space and eliminating the need for lateral expansion or excessive inter-layer spacing.
Solution Approach 2:
The design moves electrical connectivity from lateral routing to vertical through-via routing through the interposer. By establishing conductive pathways in the vertical dimension rather than requiring extended lateral traces or additional buffer layers, the z-height is minimized while maintaining full electrical connectivity between the stacked packages.
3Ease of manufacture
If thermal expansion mismatch is not addressed, then manufacturing is simpler, but warpage increases during thermal cycling
Solution Approach 1:
The interposer substrate is specifically selected with thermal expansion parameters (coefficient of thermal expansion) that match or are compatible with the die materials being mounted. By changing the material parameters of the interposer to align with the dies, thermal stress during cycling is minimized, preventing warpage while maintaining manufacturing feasibility through standard material selection processes.
Solution Approach 2:
The interposer substrate may utilize composite material constructions that combine different materials with complementary properties to achieve optimal thermal expansion matching. This composite approach allows tailoring the thermal and mechanical properties of the interposer to specifically counteract warpage tendencies while maintaining ease of manufacture through established composite fabrication techniques.
Data Source
AI summary
Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.