Stepped Gate Through-Via Isolation to Prevent Over-Etch Breakdown
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Solution Overview
Problem
Current semiconductor devices face challenges in preventing defects during the pad structure formation process, particularly in securing electrical insulation between through vias and gate electrodes, which affects the reliability and stability of the device.
Innovation Solution
A semiconductor device design incorporating a separation insulating layer with varying thicknesses and a conductive pillar structure, along with a blocking insulating layer, is proposed. The method involves forming a through via with a conductive pillar and connection portion, and using a seeding treatment with an aminosilane-based compound to ensure electrical insulation and prevent over-etching-related breakdowns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching is performed to form the through via, then structural formation is achieved, but over-etching causes breakdown and defects
Solution Approach 1:
Separation insulating layers are formed in advance within the through via structure before final etching and filling operations. These pre-formed insulating layers serve as protective barriers that prevent over-etching from causing breakdown of the gate electrodes or surrounding structures.
Solution Approach 2:
The separation insulating layers act as cushioning elements that absorb and prevent the harmful effects of over-etching. By placing these insulating layers beforehand in critical regions, the patent protects against etching-induced damage while still allowing sufficient etching to achieve proper through via formation.
2Productivity
If gate electrodes are arranged in a stepped shape for three-dimensional integration, then data storage capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The separation insulating layers are selectively applied only to specific portions of the through via structure, particularly the connection portion that interfaces with the stepped gate electrodes. This localized application provides necessary insulation without adding complexity to the entire device structure.
Solution Approach 2:
The patent addresses the three-dimensional stepped gate electrode structure by introducing separation insulating layers in the vertical dimension within the through via. This dimensional approach allows the structure to accommodate vertical stacking while maintaining electrical isolation through the insulating layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively limits and prevents defects such as punch-through and electrical insulation issues, enhancing the reliability and structural stability of the semiconductor device by ensuring proper electrical isolation and reducing the risk of over-etching-related breakdowns.
Implementation Method 1
forming a separation insulating layer on an inner wall of the first extended opening, the separation insulating layer including a first portion and a second portion
Data Source
AI summary
A semiconductor device may include gate electrodes spaced apart from each other in a first direction on a substrate and including pads in a stepped shape, a channel extending through the gate electrodes, a first through via, first and second separation insulating layers, and an insulating pattern. The gate electrodes may include second gate electrodes below a first gate electrode. The first through via may pass through and electrically connect to a first pad of the first gate electrode, pass through the second gate electrodes, and include a connection portion connected to a conductive pillar. The connection portion may contact the first pad. The first separation insulating layer may be on an upper surface of the connection portion. The second separation insulating layer may be on a bottom surface of the connection portion. The insulating pattern may be between the first through via and sidewalls of the second gate electrodes.