Through-Via Lattice Structure to Prevent Etch Contact Failures

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Solution Overview

Problem

The existing technologies for forming through-via structures in integrated circuit devices face challenges in securing stable and reliable electrical connections due to residual material from dummy device patterns, which can cause contact failures during the etching process.

Innovation Solution

The integration of a lattice structure with alternately arranged first insulating material patterns and dummy device patterns of varying sizes in the target through-region, where the dummy device patterns have a relatively low density and are uniformly distributed, helps prevent contact failures by minimizing residual material issues during the etching process for the through-via structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy device patterns are densely arranged to maintain electrical characteristics, then device performance is improved, but residual material accumulation increases causing contact failures

Engineering Contradiction:
Improvedevice performanceVSAvoidresidual material
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The dummy device patterns are segmented and alternately arranged with first insulating material patterns in a lattice structure, ensuring that each dummy pattern is isolated and surrounded by insulating material, which prevents residual material accumulation during the etching process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first insulating material patterns act as intermediary structures between adjacent dummy device patterns, providing isolation and preventing residual material from one dummy pattern from affecting neighboring patterns during etching

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12062594B2Integrated circuit device including a through-via structure
Publication Date: 2024.08.13 SAMSUNG ELECTRONICS CO LTD
  • US12062594B2 patent drawing
  • US12062594B2 patent drawing
  • US12062594B2 patent drawing

AI summary

An integrated circuit device includes: a substrate having an active surface, an inactive surface, a first region and a second region; a device structure on the active surface, and including individual devices disposed in the first region and a target through-region disposed in the second region; a multilayer wiring structure including wiring layers, wherein at least one wiring layer among the wiring layers has a landing pad overlapping the target through-region; and a through-via structure connected to the landing pad by penetrating through the second region and the target through-region, wherein the target through-region includes first insulating material patterns and dummy device patterns, wherein the first insulating material patterns each have a first area, wherein the dummy device patterns are on the active surface and each have a second area smaller than the first area, and wherein the first insulating material patterns are alternatively arranged with the dummy device patterns.