Through-Substrate Via Layout for Low-Stress Dense Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in increasing device density and reducing stress and defects in the formation of through-substrate vias and nanostructure transistors, particularly due to the integration of isolation and epitaxial structures.
Innovation Solution
The formation of through-substrate vias is improved by creating isolation structures and epitaxial source/drain regions before forming the via, which reduces stress and enhances device yield and performance, allowing for closer integration of devices without increasing defect risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If through-substrate vias are formed before isolation structures, then via formation is simpler, but stress and defects increase reducing device yield
Solution Approach 1:
Isolation structures and epitaxial source/drain regions are formed before through-substrate via formation. This preliminary action prepares the substrate to accommodate the via, reducing stress and defects during via formation while maintaining manufacturing simplicity.
Solution Approach 2:
The substrate is divided into device regions and through-via regions with isolation structures separating them. This segmentation allows independent optimization of each region, enabling via formation without compromising device yield.
2Productivity
If devices are formed closer to through-substrate vias, then device density increases, but stress and defects increase reducing performance
Solution Approach 1:
Epitaxial source/drain regions are formed in advance in the through-via regions, creating a stress-compensating structure that allows devices to be placed closer to vias without performance degradation.
Solution Approach 2:
Different regions of the substrate are given different properties: device regions contain active transistors while through-via regions contain isolation structures and epitaxial regions. This local differentiation enables close spacing without compromising device performance.
3Productivity
If minimum feature size is reduced, then integration density increases, but stress concentration increases reducing yield
Solution Approach 1:
Isolation structures and epitaxial regions are formed before via etching, creating a prepared substrate that can accommodate smaller features without stress concentration, thereby maintaining yield while increasing integration density.
Solution Approach 2:
Epitaxial source/drain regions are formed in advance to act as cushioning structures that absorb and distribute stress, preventing stress concentration even as minimum feature sizes are reduced for higher density.
Data Source
AI summary
A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming a first gate structure around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a through via extending through isolation regions and into the substrate.