Through-Via Package Structure for Delamination-Resistant 3D Integration

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in manufacturing smaller, more densely integrated semiconductor devices, particularly in maintaining structural integrity and reducing delamination risks in 3D packaging and 3D-IC devices.

Innovation Solution

A method involving the formation of conductive structures with a shrunk lower portion and a wider upper portion, surrounded by a protective layer, and connected via conductive bumps, which reduces stress concentration and delamination risk through misalignment of the interface edges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional packaging technologies are used for 3D packaging and 3D-IC devices, then device integration density can be increased, but structural integrity deteriorates and delamination risk increases

Engineering Contradiction:
Improvedevice integration densityVSAvoidstructural integrity
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The conductive structure employs an asymmetric geometry where the lower portion has a smaller cross-sectional area than the upper portion. This asymmetric design creates a tapered profile that distributes mechanical stresses more effectively throughout the structure, preventing stress concentration at any single interface and thereby maintaining structural integrity while supporting high device integration density

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The invention changes the geometric parameters of the conductive structure by varying the cross-sectional area along its height. The lower portion has a reduced cross-sectional area compared to the upper portion, creating a specific aspect ratio that optimizes stress distribution. This parameter modification allows the structure to maintain both high integration density and structural stability

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If smaller package structures are developed to package semiconductor devices, then area utilization is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepackage areaVSAvoidmanufacturing complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The conductive structure is segmented into distinct portions: a lower portion with a first cross-sectional area and an upper portion with a second cross-sectional area. This segmentation allows each portion to be optimized for its specific functional requirements while simplifying the overall manufacturing process through modular construction approaches

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12489045B2Package structure with through vias
Publication Date: 2025.12.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12489045B2 patent drawing
  • US12489045B2 patent drawing
  • US12489045B2 patent drawing

AI summary

A package structure is provided. The package structure includes a conductive structure having a first portion with a first sidewall and a second portion with a second sidewall, and the first sidewall and the second sidewall have different slopes. The package structure also includes a semiconductor chip beside the conductive structure and a protective layer laterally surrounding the conductive structure and the semiconductor chip. The protective layer covers the first sidewall of the first portion and the second sidewall of the second portion. The protective layer is made of a polymer material dispersed with fillers.