Through-Via Semiconductor Package Structure for Low-Distortion Signals

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Solution Overview

Problem

Existing leadframe packages are unsuitable for high-speed semiconductor dies due to increased mutual inductance and capacitance from narrow lead pitches, leading to signal distortion and higher packaging costs.

Innovation Solution

A semiconductor package structure with a through via passing through the semiconductor substrate, coupled to a conductive adhesive layer, which improves electrical performance and reliability by reducing resistance and enhancing signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the lead pitch is reduced to accommodate more connection pins in a smaller space, then the package size is reduced, but the mutual inductance and mutual capacitance increase causing signal distortion

Engineering Contradiction:
Improvepackage sizeVSAvoidsignal transmission quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces through-vias that extend vertically through the semiconductor substrate, adding a vertical dimension to electrical connections. This allows signal paths to be routed through the thickness of the substrate rather than relying solely on horizontal lead paths, effectively utilizing the third dimension to reduce parasitic effects while maintaining compact package dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive adhesive layer serves as an intermediary element that couples the through-vias to the leadframe structure. This intermediate conductive layer provides a low-inductance connection path between the substrate and external leads, reducing the overall parasitic inductance and capacitance in the signal path.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the number of external connection pins is increased to provide more functionality, then the functionality is improved, but the packaging cost increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidpackaging cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

By utilizing vertical through-vias through the substrate, the patent enables additional connection points without proportionally increasing package footprint. This vertical routing approach allows more functional connections to be achieved within the same planar area, reducing the need for additional external pins and associated packaging complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Length of moving object

If the lead pitch is narrowed to reduce package size, then the package becomes more compact, but the mutual inductance and mutual capacitance increase

Engineering Contradiction:
Improvelead pitchVSAvoidmutual inductance and mutual capacitance
Core Design Contradiction:
Length of moving objectVSObject-generated harmful factors

Solution Approach 1:

The through-via structure transforms horizontal current paths into vertical paths through the substrate. This dimensional change reduces the loop area for current flow, thereby minimizing mutual inductance and capacitance effects even when leads are closely spaced, allowing narrow pitch without sacrificing electrical performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive adhesive layer acts as an intermediary that provides direct vertical coupling between the through-vias and leadframe, creating short current paths that minimize the development of parasitic inductance and capacitance that would otherwise arise from narrow horizontal lead spacing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structure enhances electrical performance and reliability by minimizing signal distortion and reducing packaging costs while maintaining a compact form factor.

Implementation Method 1

The conductive adhesive layer is disposed on the second surface of the semiconductor substrate. The through via is coupled to the conductive adhesive layer.

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20250329618A1Semiconductor package structure and method for forming the same
Publication Date: 2025.10.23 MEDIATEK INC
  • US20250329618A1 patent drawing
  • US20250329618A1 patent drawing
  • US20250329618A1 patent drawing

AI summary

A semiconductor package structure and a method for forming the same are provided. The semiconductor package structure includes a semiconductor die and a conductive adhesive layer. The semiconductor die includes a semiconductor substrate, a semiconductor substrate and a through via. The semiconductor substrate has a first surface and a second surface. The semiconductor device is formed on the first surface of the semiconductor substrate. The through via is formed in such a way that it passes through the semiconductor substrate. The conductive adhesive layer is disposed on the second surface of the semiconductor substrate. The through via is coupled to the conductive adhesive layer.